Ex Parte Gunnam et al

Patent Trial and Appeal Board

Jan 25, 2018

14792982 (P.T.A.B. Jan. 25, 2018)

United States Patent and Trademark Office
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O.Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
14/792,982 07/07/2015 Kiran Kumar GUNNAM 2238-03903 6815
23505 7590
CONLEY ROSE, P.C.
575 N. Dairy Ashford Road
Suite 1102
HOUSTON, TX 77079
01/29/2018 EXAMINER
MEHRMANESH, ELMIRA
ART UNIT PAPER NUMBER
2113
NOTIFICATION DATE DELIVERY MODE
01/29/2018 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
pathou @conleyrose.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte KIRAN KUMAR GUNNAM and GWAN S. CHOI
Appeal 2017-009424
Application 14/792,982
Technology Center 2100
Before MAHSHID D. SAADAT, ALLEN R. MacDONALD, and
JOHN P. PINKERTON, Administrative Patent Judges.
MacDONALD, Administrative Patent Judge.
DECISION ON APPEAL
Appeal 2017-009424
Application 14/792,982
STATEMENT OF CASE
Appellants appeal under 35 U.S.C. § 134(a) from a final rejection of
claims 1—9. Claim 2 has been objected to as being dependent upon a
rejected base claim, but otherwise containing allowable subject matter if
rewritten to overcome the double patenting rejections and in independent
form. We have jurisdiction under 35 U.S.C. § 6(b).
We affirm.
Exemplary Claim
Exemplary claim 1 under appeal reads as follows (emphasis added);
1. A low density parity check (LDPC) code decoder,
comprising:
decoding circuitry configured to process blocks of an
LDPC matrix, the decoding circuitry comprising:
a control unit that controls processing by the
decoding circuitry, the control unit configured to cause
the decoding circuitry to process blocks of a layer of the
LDPC matrix out of order.
App. Br. 11 (Claims Appendix).
Rejections on Appeal
1. The Examiner rejected claims 1—9 on numerous grounds of non-
statutory obviousness-type double patenting as not being patentably distinct
from claims in numerous patents. See Ans. 2—5.1
1 Appellants do not appeal the double patenting rejections within the time
provided. See App. Br. 7 (“The Examiner has agreed that response to the
nonstatuory double patenting rejections . . . can be delayed until the . . .
rejections under § 103 . . . have been overcome”); see also 37 C.F.R.
§ 41.31 (a)(1). Therefore, we affirm these rejections pro forma. Except for
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Application 14/792,982
2. The Examiner rejected claims 1 and 3—9 under 35 U.S.C. § 103(a)
as being unpatentable over Yokokawa et al. (US 2005/0240853 Al;
published Oct. 27, 2005) (“Yokokawa”) and Yueng et al. (US 7,958,427 Bl;
issued June 7, 2011) (“Yueng”).* 2
Issue on Appeal
Did the Examiner err in rejecting claim 1 as being obvious?
PRINCIPLES OF LAW
The mere existence of differences between the prior art and the claim
does not establish non-obviousness. See Dann v. Johnston, 425 U.S. 219,
230 (1976). Instead, the relevant question is “whether the difference
between the prior art and the subject matter in question is a [difference]
sufficient to render the claimed subject matter unobvious to one skilled in
the applicable art.” Dann, 425 U.S. at 228 (internal quotations and citations
omitted). Indeed, the Supreme Court made clear that when considering
obviousness, “the analysis need not seek out precise teachings directed to the
specific subject matter of the challenged claim, for a court can take account
of the inferences and creative steps that a person of ordinary skill in the art
would employ.” KSRInt’l Co. v. Teleflex Inc., 550 U.S. 398, 418 (2007).
our ultimate decision, these rejections of these claims are not discussed
further herein.
2 The patentability of claims 3—9 is not separately argued from that of claim
1. See App. Br. 9. Thus, except for our ultimate decision, claims 3—9 are
not discussed further herein.
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Appeal 2017-009424
Application 14/792,982
ANALYSIS
We have reviewed the Examiner’s rejections in light of Appellants’
arguments that the Examiner has erred. We disagree with Appellants’
contention that the Examiner erred. Instead, we concur with the conclusions
reached by the Examiner.
Appellants contend the Examiner erred in rejecting claim 1 under
35 U.S.C. § 103(a) because:
Both Yeung col. 4, lines 15-50 and Yeung col. 8, line 36 to col.
9, line 26 appear to describe out of order decoding of received
data frames in the sense that frame processing is initiated in the
order that the frames are received, but completion of processing
may be out of order if processing of later received frames
requires fewer resources than is required by earlier received
frames.
In distinction to this teaching of Yeung, claim 1 requires
processing “blocks of a layer of an LDPC matrix out of order.”
Processing complete data frames or disk sectors out of order,
as taught by Yeung (i.e., in order initiation and out of order
completion) is unrelated to processing the blocks of a layer of
an LDPC matrix out of order, at least because the data frames
of Yeung are not blocks of a layer (i.e., internal sub-parts of
internal sub-parts) of an LDPC matrix. Yeung fails to teach
that blocks of an LDPC code matrix or any other sub-elements
of a data frame are processed out of order relative to other sub­
elements of the data frame, but rather merely teaches that data
frames may be processed through the decoder in other than the
order received. In fact, Yeung implies that each frame or sector
corresponds to an LDPC matrix. Accordingly, Yeung appears
to teach pipelined processing of different LDPC matrices that
may result in completion of processing of a later received matrix
before completion of processing of an earlier received matrix.
Thus, at best Yeung teaches pipelined processing a macro level,
while the present limitations of claim 1 recite out of order
processing at a much lower level that is not even conceived of
by Yeung. Therefore, Appellant respectfully submits that the
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Appeal 2017-009424
Application 14/792,982
processing of Yeung fails to teach or even suggest processing
blocks of a layer of an LDPC matrix out of order.
App. Br. 8—9 (Appellants’ citations and emphasis omitted; panel’s emphasis
added).
This argument is not persuasive. We agree with the Examiner that
Yokokawa teaches a LDPC decoder configured to process blocks of layers
of an LDPC matrix (see Ans. 8—9 (citing Yokokawa H 21, 110)), and that
Yueng teaches a LDPC decoder configured to decode a data collection (i.e.,
data frames or data sectors) out of order. See Ans. 9—10 (citing Yeung 2:45—
52; 6:15—29; 8:36—67; 9:1—26). Appellants’ argument that Yueng merely
teaches processing data frames out of order, as opposed to processing blocks
of a layer of a LDPC matrix out of order, is not persuasive, as we conclude
that modifying the LDPC decoder taught in Yokokawa to process blocks of
a layer of a LDPC matrix out of order would have been obvious to one of
ordinary skill in the art in light of Yeung’s LDPC decoder configured to
process data out of order. See KSR, 550 U.S. at 417 (“When a work is
available in one field of endeavor, design incentives and other market forces
can prompt variations of it, either in the same field or a different one. If a
person of ordinary skill can implement a predictable variation, § 103 likely
bars its patentability.”). Therefore, Appellants have not shown that the
Examiner erred in finding that the combination of cited references teaches or
suggests the limitations of claim 1.
CONCLUSIONS
(1) The Examiner has not erred in rejecting claims 1—9 for numerous
grounds of non-statutory obviousness-type double patenting.
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Application 14/792,982
(2) The Examiner has not erred in rejecting claims 1 and 3—9 as being
unpatentable under 35 U.S.C. § 103(a).
(3) Claims 1—9 are not patentable.
DECISION
We affirm the Examiner’s rejections of claims 1—9 for numerous
grounds of non-statutory obviousness-type double patenting.
We affirm the Examiner’s rejection of claims 1 and 3—9 as being
unpatentable under 35 U.S.C. § 103(a).
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(l)(iv).
AFFIRMED
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