Ex Parte Gschwind

Patent Trial and Appeal Board

Dec 18, 2013

11762137 (P.T.A.B. Dec. 18, 2013)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
11/762,137 06/13/2007 MICHAEL GSCHWIND YOR920070109US1
(163-174)
1231
49267 7590 12/19/2013
TUTUNJIAN & BITETTO, P.C.
425 Broadhollow Road, Suite 302
Melville, NY 11747
EXAMINER
TREAT, WILLIAM M
ART UNIT PAPER NUMBER
2183
MAIL DATE DELIVERY MODE
12/19/2013 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________

Ex parte MICHAEL GSCHWIND
____________

Appeal 2011-004791
Application 11/762,137
Technology Center 2100
____________

Before CAROLYN D. THOMAS, ELENI MANTIS MERCADER, and
JOHN A. EVANS, Administrative Patent Judges.

MANTIS MERCADER, Administrative Patent Judge.

DECISION ON APPEAL

Appeal 2011-004791
Application 11/762,137

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STATEMENT OF THE CASE
Appellant appeals under 35 U.S.C. § 134(a) from a final rejection of
claims 1-20. We have jurisdiction under 35 U.S.C. § 6(b).
We reverse.

THE INVENTION
Appellant’s claimed invention is directed to a plurality of port groups,
operatively coupled to a plurality of multi-bit storage cells, responsive to
physical register identifiers. The plurality of port groups is responsive to
respective ones of a plurality of thread identifiers. Each of the plurality of
thread identifiers are for uniquely identifying a particular thread from among
a plurality of threads. See Abstract.
Independent claim 1, reproduced below, is illustrative of the subject
matter on appeal.
1. An apparatus for a register file, comprising:
a plurality of multi-bit storage cells for storing a plurality of bits
respectively corresponding to a plurality of threads; and
a plurality of port groups, operatively coupled to said plurality of
multi-bit storage cells, responsive to physical register identifiers, each port
group comprising a group of ports sharing a common selection circuit such
that all ports within the port group access registers from a common subset of
registers;
wherein said plurality of port groups are responsive to respective ones
of a plurality of thread identifiers, each of the plurality of thread identifiers
for uniquely identifying a particular thread from among a plurality of
threads.
REFERENCES and REJECTION
The Examiner rejected claims 1-20 under 35 U.S.C.§ 103(a) as
unpatentable over Aipperspach (U.S. Pat. 6,629,236 B1, Sep. 30, 2003) in
Appeal 2011-004791
Application 11/762,137

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view of the Examiner’s Final Action (dated 9/20/2006) in the application file
of Aipperspach (U.S. Pub. No. 2003/0200424 A1, Oct. 23, 2003).

ISSUE
The issue is whether the Examiner erred in finding that Aipperspach
teaches the limitation of “a plurality of port groups . . . each port group
comprising a group of ports sharing a common selection circuit such that all
ports within the port group access registers from a common subset of
registers” as recited in claim 1; the limitation of “thread group identifiers” as
recited in claim 9; and the limitation of “at least two port groups . . .
responsive to a common selection signal” as recited in claim 18.

ANALYSIS
Claims 1-8
Appellant argues, inter alia, that Aipperspach does not teach the
limitation of “a group of ports sharing a common selection circuit such that
all ports within the port group access registers from a common subset of
registers” as recited in claim 1 (Br. 13).
We agree with Appellant. Claim 1 recites “a plurality of port groups .
. . each port group comprising a group of ports sharing a common selection
circuit such that all ports within the port group access registers from a
common subset of registers.” At best, Aipperspach’s Figure 5 teaches a
plurality of ports 510, but we find no teaching of a plurality of port groups
wherein each port group comprises a group of ports sharing a common
selection circuit.
Appeal 2011-004791
Application 11/762,137

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Similarly, claim 18 recites “at least two port groups . . . responsive to
a common selection signal.”
Accordingly, we reverse the Examiner’s rejections of independent
claims 1 and 18. We also reverse the Examiner’s rejections of claims 2-8
and 19-20 for the same reasons.

Claims 9-17
Appellant argues that Aipperspach does not teach thread group
identifiers (Br. 14). We agree with Appellant that from the record before us,
Aipperspach does not teach thread group identifiers.
Thus, we reverse the Examiner’s rejection of claim 9 and for the same
reasons, the rejections of claims 10-17.

CONCLUSION
The Examiner erred in finding that the Aipperspach teaches the
limitation of “a plurality of port groups . . . each port group comprising a
group of ports sharing a common selection circuit such that all ports within
the port group access registers from a common subset of registers” as recited
in claim 1; the limitation of “thread group identifiers” as recited in claim 9;
and the limitation of “at least two port groups . . . responsive to a common
selection signal” as recited in claim 18.

Appeal 2011-004791
Application 11/762,137

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DECISION
The Examiner’s decision rejecting claims 1-20 is reversed.

REVERSED

ELD