Ex Parte Gruber et alDownload PDFPatent Trial and Appeal BoardNov 9, 201712850505 (P.T.A.B. Nov. 9, 2017) Copy Citation United States Patent and Trademark Office UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O.Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 12/850,505 08/04/2010 Matei Gruber I004-P10024US 9984 148415 7590 Key sight Technologies, Inc. In care of: CPA Global 900 Second Avenue South Suite 600 Minneapolis, MN 55402 EXAMINER SWEET, LONNIE V ART UNIT PAPER NUMBER 2467 NOTIFICATION DATE DELIVERY MODE 11/14/2017 ELECTRONIC Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the following e-mail address(es): key sightdocketing @ cpaglobal. com notice, legal @key sight, com PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE BEFORE THE PATENT TRIAL AND APPEAL BOARD Ex parte MATEI GRUBER and ADRIAN STANCIU Appeal 2015-003071 Application 12/850,505 Technology Center 2400 Before: ROBERT E. NAPPI, ELENI MANTIS MERCADER, and STEVEN M. AMUNDSON, Administrative Patent Judges. MANTIS MERCADER, Administrative Patent Judge. DECISION ON APPEAL STATEMENT OF THE CASE Appellants appeal under 35 U.S.C. § 134 from a Final Rejection of claims 1—9. We have jurisdiction under 35 U.S.C. § 6(b). We affirm. Appeal 2015-003071 Application 12/850,505 CLAIMED SUBJECT MATTER The claimed invention is directed to high precision packet generation using a hardware time stamp counter. Spec. para. 40. Claim 1, reproduced below, is illustrative of the claimed subject matter: 1. A network testing system having at least one network card, the network card including a processor, a hardware counter, a memory and a network communications unit, the network testing system coupled with a network, the network testing system having instructions stored thereon which when executed cause the network testing system to perform operations comprising: receiving user selection to create a network test receiving test information from the user, the test information including a packet transmission rate and packet creation information calculating a packet transmission interval based on the packet transmission rate, wherein the packet transmission interval defines how often packets will be sent to achieve the user specified packet transmission rate receiving user selection to execute the network test transmitting packets specified in the network test over the network at the packet transmission rate, including preparing a packet including at least a payload and a header according to the packet creation information directly accessing and checking the hardware counter to learn if the packet transmission interval has elapsed when the packet transmission interval has elapsed, sending the packet over the network. REFERENCES The prior art relied upon by the Examiner in rejecting the claims on US 6,961,285 B2 appeal is: Niemiec et al. 2 Nov. 1,2005 Appeal 2015-003071 Application 12/850,505 Masuda et al. Tripathi et al. Hughes et al. Cidon et al. Zampetti et al US 7,433,069 B2 US 7,689,702 B1 US 2001/0037434 Al US 2007/0195707 Al US 2011/0134766 Al Oct. 7, 2008 Mar. 30, 2010 Nov. 1,2001 Aug. 23, 2007 June 9,2011 REJECTIONS Claims 1, 2, 4, 5, 7, and 8 stand rejected under 35 U.S.C § 103(a) as being unpatentable over Cidon in view of Zampetti, Masuda, and Niemiec. Claims 3, 6, and 9 stand rejected under 35 U.S.C § 103(a) as being unpatentable over Cidon in view of Zampetti, Masuda, Niemiec, and Tripathi. ISSUE The pivotal issue is whether the Examiner erred in finding that the combination of Cidon in view of Zampetti, Masuda, and Niemiec teaches or suggests the limitation of “directly accessing and checking the hardware counter to learn if the packet transmission interval has elapsed” as recited in claim 1. ANALYSIS We adopt the Examiner’s findings in the Final Rejection and the Answer and add the following primarily for emphasis. Claims 1, 4, and 7 Appellants first argue that Niemiec does not teach a specific kind of counter, and accordingly, there is no teaching of “directly accessing a hardware counter” as claimed (Br. 7). Appellants assert that the kind of counter, its location, and how it is accessed are not disclosed in Niemiec (Br. 3 Appeal 2015-003071 Application 12/850,505 7). As such, Appellants conclude that Niemiec’s disclosure is insufficient to teach the claimed “directly accessing and checking the hardware counter to learn if the packet transmission interval has elapsed” (Br. 7). Appellants further assert that Niemiec only provides brief references to a “time counter” and a “local counter” without any supporting detail (Br. 8). According to Appellants, the kind of counter used in Niemiec is unknown because there is no description of any kind of time counter (Br. 8). Appellants assert that the time counter and local counter in Niemiec could be software counters or virtual clocks, which is insufficient to disclose the specifically claimed “hardware counter” (Br. 8). The Examiner finds, and we agree, that Niemiec does teach directly accessing a hardware counter which is described as the time counter of the device 104 in Figure 1 of Niemiec (Ans. 5 citing Fig. 1 and col. 10,11. 44— 53). Niemiec teaches that the time clock in an alternate embodiment may be a clock internal to the device 104 and may be checked by device 104 to determine if a transmission time has elapsed (id.). The Examiner reasonably concludes that by being an internal component of the device 104, any accessing of this component by device 104 to check the time is viewed as a technique involving direct access (Ans. 5). The Examiner further finds that the counter and internal clock are hardware, because in Niemiec the processor 110, which is hardware, provides the functionality of each of the embodiments, which comprises the function of the internal clock and counter for the device 104, in conjunction with the operating instructions 112 in memory 116 (Ans. 5; Fig. 1, col. 4,11. 19—25). In KSR, the Supreme Court held that “if a technique has been used to improve one device, and a person of ordinary skill in the art would recognize 4 Appeal 2015-003071 Application 12/850,505 that it would improve similar devices in the same way, using the technique is obvious unless its actual application is beyond his or her skill.” See KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007). The Supreme Court has also determined the conclusion of obviousness can be based on the interrelated teachings of multiple patents, the effects of demands known to the design community or present in the marketplace, and the background knowledge possessed by a person having ordinary skill in the art. Id. at 418. The skilled artisan is “a person of ordinary creativity, not an automaton.” Id. at 421. Appellants have not presented any evidence demonstrating that the modification would have been “uniquely challenging or difficult for one of ordinary skill in the art.” See Leapfrog Enters., Inc. v. Fisher-Price, Inc., 485 F.3d 1157, 1162 (Fed. Cir. 2007) (citing KSR, at 418). Thus, we further agree with the Examiner’s additional supporting evidence of the ability of “directly accessing a hardware counter” as being widely well known in the art as taught by Hughes of “a Time Stamp Counter (TSC) register 330, which is a hardware counter employed by processor 10 connected to circuitry described in Hughes as a bus interface 37” (Ans. 5; Fig. 21, para. 212). More particularly, Hughes teaches that this TSC register 330 measures time elapsed and may be directly accessed using the bus interface 37 (Ans. 5; para. 212). Accordingly, we agree with the Examiner that Niemiec teaches or suggests the limitation of “directly accessing and checking the hardware counter to learn if the packet transmission interval has elapsed” and/or in the alternative Hughes teaches that such a hardware counter would have been widely known by skilled artisans who could substitute one type of counter for another as alternative counters performing the same function. 5 Appeal 2015-003071 Application 12/850,505 Claims 2, 5, and 8 Appellants further argue that Zampetti fails to disclose a time stamp counter (TSC) register of a processor as claimed (Br. 8). That is, the “local clock” of Zampetti is not “a time stamp counter (TSC) register of a processor” (Br. 8). We do not agree. We agree with the Examiner’s findings in the Answer (Ans. 7). In particular, we agree with the Examiner that the claims recite that “the hardware counter is a time stamp counter (TSC) register of the processor included in the network card,” wherein the term “of’ is broadly but reasonably interpreted as meaning “relating to” or “connected with” (as defined in Merriam Webster) the processor, and thus as long as the processor is using the register or is connected to the TSC register for use, the register relates to the processor (Ans. 7). Furthermore, as alternatively found supra, as well known in the art, Hughes teaches in Figure 21a Time Stamp Counter (TSC) register 330, which is a hardware counter employed by processor 10 connected to circuitry described in Hughes as a bus interface 37 (Ans. 7, Fig. 21, para. 212). Claims 3, 6, and 9 Appellants do not dispute that Tripathi teaches a kernel routine call. However, Appellants argue that claims 3, 6, and 9 recite “wherein the directly accessing and checking the hardware counter comprises making a call to a routine in a kernel of an operating system executing on the computing device” and as such, the kernel routine call must directly access a hardware time counter (Br. 9-10). According to Appellants, Tripathi does not disclose using a kernel routine call to access and check a hardware time counter (Br. 10). 6 Appeal 2015-003071 Application 12/850,505 We agree with the Examiner that Tripathi teaches the act of making a call to a routine in a kernel of an operating system executing on the network card of the computer device (Final Rej. 11; Ans. 9; Fig. 2, col. 6,11. 10-26). The Examiner relies on Niemiec for teaching directly accessing and checking the hardware counter to determine if a time has elapsed (Ans. 9). “[0]ne cannot show non-obviousness by attacking references individually where . . . the rejections are based on combinations of references.” In re Keller, 642 F.2d413, 426 (CCPA 1981). Accordingly, we affirm the Examiner’s rejections of claims 1—9. CONCLUSION The Examiner did not err in finding that the combination of Cidon in view of Zampetti, Masuda, and Niemiec teaches or suggests the limitation of “directly accessing and checking the hardware counter to learn if the packet transmission interval has elapsed” as recited in claim 1. DECISION The Examiner’s rejection of claims 1—9 is affirmed. No time period for taking any subsequent action in connection with this appeal may be extended under 37 C.F.R. § 1.136(a). See 37 C.F.R. § 1.136(a)(l)(iv). AFFIRMED 7 Copy with citationCopy as parenthetical citation