Ex Parte Graef

Patent Trial and Appeal Board

Jun 16, 2016

12750871 (P.T.A.B. Jun. 16, 2016)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE
121750,871 03/31/2010
57299 7590 06/20/2016
Kathy Manke
A vago Technologies Limited
4380 Ziegler Road
Fort Collins, CO 80525
FIRST NAMED INVENTOR
Nils Graef
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
L09-0749US1 9589
EXAMINER
MCCARTHY, CHRISTOPHER S
ART UNIT PAPER NUMBER
2113
NOTIFICATION DATE DELIVERY MODE
06/20/2016 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address( es):
kathy.manke@broadcom.com
patent.info@broadcom.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte NILS GRAEF
Appeal2014-005930
Application 12/750,871
Technology Center 2100
Before DEBRA K. STEPHENS, JASON V. MORGAN, and
MICHAEL J. ENGLE, Administrative Patent Judges.
STEPHENS, Administrative Patent Judge.
STATEMENT OF THE CASE
Appellant appeals under 35 U.S.C. § 134(a) from a Final Rejection of
claims 1-22. We have jurisdiction under 35 U.S.C. § 6(b).
We AFFIRM-IN-PART.
STATEMENT OF THE INVENTION
According to Appellants, the claims are directed to signal processing
techniques and, more specifically, a hard input low density parity check
Appeal2014-005930
Application 12/750,871
decoder (Abstract; Spec. if 2). Claims 1 and 10, reproduced below, are
representative of the claimed subject matter:
1. A hard-decision decoder for decoding one or more error-
correcting (EC) codewords, said decoder comprising:
a bit-flipping decoder that flips one or more bit nodes
connected to one or more unsatisfied parity checks; and
a syndrome calculator that performs a parity check to
determine whether said bit-flipping decoder has converged on
a valid codeword, wherein said bit-flipping decoder and said
syndrome calculator share one or more logic elements.
10. A method for decoding one or more error-correcting (EC)
codewords, said method comprising:
flipping one or more bit nodes connected to one or more
unsatisfied parity checks; and
updating one or more parity check equations associated with
said one or more bit nodes each time said one or more bit
nodes are flipped.
REFERENCES
The prior art relied upon by the Examiner in rejecting the claims on
appeal is:
Tran
Yedidia
O'Neill
US 2006/0085720 Al
US 2006/0161830 Al
US 2009/0164874 Al
REJECTIONS
Apr. 20, 2006
July 20, 2006
June 25, 2009
Claims 1-3, 8-17, 21, and 22 stand rejected under 35 U.S.C. § 102(b)
as being anticipated by Yedidia (Final Act. 2--4).
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Application 12/750,871
Claims 4---6 and 18-20 stand rejected under 35 U.S.C. § 103(a) as
being unpatentable over Y edidia and 0 'Neill (Final Act. 4--5).
Claim 7 stands rejected under 35 U.S.C. § 103(a) as being
unpatentable over Yedidia, O'Neill, and Tran (Final Act. 5---6).
ISSUES
35 U.S.C. § 102(b): Claims 1-3, 8-17, 21, and 22
Appellants argue their invention is not anticipated by Yedidia (App.
Br. 3-7). The issues presented by the arguments are:
Issue 1: Has the Examiner erred in finding Y edidia discloses "a
syndrome calculator that performs a parity check to determine whether said
bit-flipping decoder has converged on a valid codeword, wherein said bit-
flipping decoder and said syndrome calculator share one or more logic
elements," as recited in claim 1?
Issue 2: Has the Examiner erred in finding Y edidia discloses
"wherein said flipping step and said performing step use one or more
common logic elements," as recited in claim 15?
Issue 3: Has the Examiner erred in finding Y edidia discloses
"updating one or more parity check equations associated with said one or
more bit nodes each time said one or more bit nodes are flipped," as recited
in claim 1 O?
ANALYSIS
Issue 1:
Appellants contend the Examiner has not specifically set forth where
Y edidia discloses the recited syndrome calculator because the only
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Application 12/750,871
paragraphs cited by the Examiner do not disclose Y edidia' s termination
checker 752 "performs a parity check" (App. Br. 4). Rather, Appellants
argue, Yedidia discloses "termination checker 752 determines whether the
currently most reliable bit estimates correspond to a codeword of the error-
correcting code, or whether another termination condition has been reached"
(App. Br. 4 ). Appellants further assert Y edidia does not disclose any of the
logic elements that calculate the syndrome, and more specifically, does not
disclose a bit-flipping decoder and a syndrome calculator share one or more
logic elements (id.).
Pointing to Appellants' Specification (see Spec. i-fi-18, 19, and 61), the
Examiner determines a "logic element" is broadly defined by Appellants and
thus, may be interpreted as any element of a system, including a processor
and a memory, "both of which are implicitly shared" and including
connections which are shared between components (Ans. 6-7).
We agree with the Examiner's interpretation of "logic element."
Appellants have not explicitly defined "logic element" in their Specification.
Although Appellants contend paragraph 8 of their Specification which states
"shared logic elements may comprise,for example, cross connection circuit
elements (such as Barrel shifters), exclusive OR gates and/or memory
elements" (emphases added) supports their assertion that memory elements
are not overall memory, we are not persuaded. We note the description uses
terms such as "may" and "for example" and thus, does not limit the term
"logic element." Further, as the term "element" is not defined explicitly, we
are not persuaded, taking a broad, but reasonable interpretation in light of
the Specification, a "memory element" excludes an overall memory.
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Furthermore, with respect to claim 1, we are not persuaded by
Appellants' argument that the logic elements are not shared (App. Br. 5).
Specifically, Appellants' proffer a definition of "shared," without evidence
that this would have been the definition as understood by an ordinarily
skilled artisan, at the time of the invention. Indeed, we look to Merriam-
Webster Collegiate Dictionary, and construe the term "share" as "to partake
of, use, experience, occupy, or enjoy with others" (Merriam-Webster
Collegiate Dictionary 1144 (11th ed. 2007) ). It follows, in light of this
interpretation, we find Y edidia' s various elements share logic as all the
elements, including the memory and connection elements such as the control
block. As set forth in Yedidia, the control block is shared, and specifically,
the reliability assigner is shared between the sub-decoder and the
termination checker (Yedidia i-fi-196-98). Thus, we find the sub-decoder and
the termination checker disclosed in Y edidia share one or more logic
elements because the logic elements partake of or use (and even are "joined"
with) each other. Accordingly, we are not persuaded by Appellants'
arguments that the Examiner's interpretation of the disputed recitation is in
error. It follows, we are not persuaded by Appellants' arguments that
Y edidia fails to disclose "a syndrome calculator that performs a parity check
to determine whether said bit-flipping decoder has converged on a valid
codeword, wherein said bit-flipping decoder and said syndrome calculator
share one or more logic elements," as recited in claim 1.
Issue 2:
With respect to claim 15, Appellants' argue Y edidia does not disclose
the recited "a flipping step and a performing a parity check step using one or
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Application 12/750,871
more common logic elements" (App. Br. 3-5). The term "common" is not
defined explicitly in Appellants' Specification and as set forth above, the
term "logic elements" also is not defined explicitly. Appellants have not
proffered sufficient evidence or argument to persuade us of error in the
Examiner's findings that Yedidia discloses the flipping step and the
performing a parity check step, use one or more common logic elements (id.;
Final Act. 3).
Issue 3:
With respect to claim 10, Appellants argue unlike the Gallagher B
algorithm of Y edidia, which recalculates all check equations for each
iteration from scratch, the present invention discloses every time an
information bit is flipped, its four related parity check equations are updated
(App. Br. 5). Specifically, according to Appellants, the invention as recited
in claim 10 requires "updating one or more parity check equations
associated with said one or more bit nodes each time said one or more bit
nodes are flipped" (id. at 4).
The Examiner finds "calculating after each iteration 'updates' the
accuracy of the equation, and the specification does not disqualify 'starting
from scratch' the calculations of the equation" (Ans. 7). We agree with the
Examiner that the claim does not preclude calculating from scratch, the
parity check equations associated with the bit nodes. Indeed, even
construing "update" as asserted by Appellant, calculating the parity check
equations from scratch is incorporating new or more accurate information in
the parity check equations (see Reply Br. 6).
Appellants argue the Examiner has not shown Y edidia discloses the
parity check equations are updated each time the bit node( s) are flipped in
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reliance upon discussion of a Gallagher algorithm in Y edidia (App. Br. 5-6).
We agree Y edidia discloses updating of values in the decoder (Final Act. 7).
Specifically, Yedidia describes that in a bit-flipping (BF) decoder, "[a]t
every iteration, the estimates for each symbol are updated in parallel"
(Y edidia i-f 66). Y edidia further describes "at each iteration, the syndrome
for each parity check is computed" and "[i]f a number of those parity checks
greater than a pre-defined threshold are unsatisfied, then the corresponding
bit is flipped" (id. i-f 29). However, the Examiner has not specifically
identified where Y edidia describes the updating of the parity check
equations occurs each time one or more bit nodes are flipped. Thus, we are
constrained to find Appellants' arguments that Y edidia fails to disclose
"updating one or more parity check equations associated with said one or
more bit nodes each time said one or more bit nodes are flipped," as recited
in claim 10, are persuasive.
Appellants' arguments with respect to claims 8 and 21 (App. Br. 7)
are not persuasive as Appellants have not proffered sufficient evidence or
argument to persuade us Y edidia does not disclose "updating parity checks,"
as recited in claim 8 and 21.
Accordingly, we are not persuaded the Examiner erred in finding
Y edidia discloses the invention as recited in independent claims 1 and 15 and
dependent claims 2, 3, 8, 9, 16, 17, 21, and 22, not separately argued.
Therefore, we sustain the rejection of claims 1-3, 8, 9, 15-17, 21, and 22
under 35 U.S.C. § 102(b) for anticipation by Yedidia.
We, however, are constrained to reverse the Examiner's rejection of
independent claim 10 under 35 U.S.C. § 102(b) for anticipation by Yedidia.
Claims 11-14 stand with independent claim 10 from which they depend.
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35 U.S.C. § 103(a): Claims 4-6 and 18-20
Appellants assert their invention as recited in claims 6 and 20 are not
obvious over Yedidia and O'Neill because Yedidia does not teach the
claimed shared logic elements and 0 'Neill does not disclose the logic
elements are shared (App. Br. 6-7).
We are not persuaded. As set forth above with respect to claim 1, we
are not persuaded by Appellants' arguments that Y edidia fails to disclose
shared logic elements. Appellants have not persuaded us the combination of
Yedidia and O'Neill fails to teach "said shared logic elements comprise one
or more of cross connection circuit elements, exclusive OR gates and
memory elements," as recited in claims 6 and similarly recited in claim 20.
Therefore, we are not persuaded the Examiner erred in rejecting claims 6
and 20.
Appellants did not separately argue claims 4, 5, 18, and 19. Thus,
these claims fall with their respective independent claims, claims 1 and 15.
Accordingly, we sustain the rejection of claims 4---6 and 18-20 under
35 U.S.C. § 103(a) for obviousness over Yedidia and O'Neill.
35 U.S.C. § 103(a): Claim 7
Appellants assert their invention is not obvious over Yedidia, O'Neill,
and Tran because Y edidia does not disclose the claimed shared logic
elements comprise cross connection circuit elements comprising Barrel
shifters and Tran does not disclose shared logic elements (App. Br. 7). We
are not persuaded. As set forth above, we are not persuaded Y edidia fails to
disclose shared logic elements. As the Examiner relies on Tran for teaching
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the cross connection elements comprise Barrel shifters (Final Act. 6),
Appellants have not persuaded us the combination fails to teach "said cross
connection circuit elements comprise Barrel shifters," as recited in claim 7.
Therefore, we sustain the rejection of claims 7 under 35 U.S.C. § 103(a) for
obviousness over Yedidia, O'Neill, and Tran.
DECISION
The Examiner's rejection of claims 1-3, 8, 9, 15-17, 21, and 22 under
35 U.S.C. § 102(b) as being anticipated by Yedidia is affirmed.
The Examiner's rejection of claims 10-14 under 35 U.S.C. § 102(b)
as being anticipated by Y edidia is reversed.
The Examiner's rejection of claims 4---6 and 18-20 under 35 U.S.C.
§ 103 (a) as being unpatentable over Y edidia and 0 'Neill is affirmed.
The Examiner's rejection of claims 7 under 35 U.S.C. § 103(a) as
being unpatentable over Yedidia, O'Neill, and Tran is affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(l )(iv).
AFFIRMED-IN-PART
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