Ex Parte Goyal et alDownload PDFPatent Trial and Appeal BoardMar 25, 201512495336 (P.T.A.B. Mar. 25, 2015) Copy Citation UNITED STATES PATENT AND TRADEMARK OFFICE UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 12/495,336 06/30/2009 Suresh Goyal ALU/130137-3 2644 46363 7590 03/25/2015 WALL & TONG, LLP/ ALCATEL-LUCENT USA INC. 25 James Way Eatontown, NJ 07724 EXAMINER NGUYEN, STEVE N ART UNIT PAPER NUMBER 2117 MAIL DATE DELIVERY MODE 03/25/2015 PAPER Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE _____________ BEFORE THE PATENT TRIAL AND APPEAL BOARD _____________ Ex parte SURESH GOYAL, MICHELE PORTOLAN, and BRADFORD VAN TREUREN _____________ Appeal 2013-001093 Application 12/495,336 Technology Center 2100 ______________ Before ROBERT E. NAPPI, DEBRA K. STEPHENS, and BRUCE R. WINSOR, Administrative Patent Judges. NAPPI, Administrative Patent Judge. DECISION ON APPEAL This is a decision on appeal under 35 U.S.C. § 134(a) of the rejection of claims 1 through 22. We affirm. INVENTION The invention is directed to a method for testing a portion of a system under test (SUT) via a scan chain of the SUT. See Abstract of Appellants’ Specification. Claim 1 is illustrative of the invention and reproduced below: 1. An apparatus configured to test at least a portion of a system under test comprising a scan chain, the apparatus comprising: a processor comprising a set of instructions configured to test at least a portion of the system under test, wherein the set of Appeal 2013-001093 Application 12/495,336 2 instructions comprises a plurality of processor instructions associated with an Instruction Set Architecture (ISA) of the processor and a plurality of test instructions; wherein the scan chain comprises a plurality of physical elements, wherein the scan chain is represented using a plurality of logical segments representing the physical elements of the scan chain; wherein at least one of the test instructions is configured to define a scan operation to be executed on at least one of the logical segments representing the scan chain. REJECTIONS AT ISSUE The Examiner has rejected claims 1 through 7, 11 through 18, 21 and 22 under 35 U.S.C. § 103(a) as being unpatentable over Jacobson (US 6,195,774 B1) and Huisman (US 7,139,950 B2). Final Office Action 4–11.1 The Examiner relies on the SPARC Architecture Manual (hereinafter referred to as SPARC) as a teaching reference for features inherent in Jacobson. Final Office Action 4. The Examiner has rejected claims 8 through 10 under 35 U.S.C. § 103(a) as being unpatentable over Jacobson, Huisman, and Solt (US 7,539,915 B1). Final Office Action 11–12. The Examiner has rejected claim 19 under 35 U.S.C. § 103(a) as being unpatentable over Jacobson, Huisman, and Rozas (US 7,089,404 B1). Final Office Action 13. 1 Throughout this opinion, we refer to the Appeal Brief filed September 13, 2012, Reply Brief filed October 17, 2012, the Final Office Action mailed May 30, 2012, and the Examiner’s Answer mailed September 28, 2012. Appeal 2013-001093 Application 12/495,336 3 The Examiner has rejected claim 20 under 35 U.S.C. § 103(a) as being unpatentable over Jacobson, Huisman, and Bronte (US 6,061,709). Final Office Action 13–14. ISSUES Appellants argues on pages 12 through 17 of the Appeal Brief, and pages 2 through 4 of the Reply Brief that the Examiner’s obviousness rejection of representative independent claim 1 is in error. The issues presented by these arguments are: a) Did the Examiner err in finding the combination of Jacobson and, Huisman fails to teach or suggest a set of instructions including a plurality of processor instructions associated with an ISA and a plurality of test instructions as recited in representative claim 1? b) Did the Examiner err in finding the combination of Jacobson and, Huisman fails to teach or suggest the test instructions is configured to define a scan operation to be executed on at least one of the logical segments representing the scan chain as recited representative claim 1? ANALYSIS We have reviewed Appellants’ arguments in the Briefs, the Examiner’s rejection and the Examiner’s response to the Appellants’ arguments. We disagree with Appellants’ conclusion that the Examiner erred in rejecting the claims under 35 U.S.C. § 103(a). Appeal 2013-001093 Application 12/495,336 4 With respect to the first issue, Appellants argue Jacobson and the SPARC architecture manual teach a CPU Instruction Set Architecture (IAS) but do not teach a set of instruction associated with an ISA and a plurality of test instructions. Appeal Br. 13. The Examiner provided a comprehensive explanation to Appellants’ arguments, finding that Jacobson teaches a computer system in which there is an ISA and test instructions (Boundary Scan Test (BST) instructions). Answer 2. We concur. Further, we are not persuaded by Appellants’ argument that Jacobson “merely indicates that two different types of instructions may be executed by the same processor at different times, not that the two different types of instructions co-exist within the processor as a set of instructions configured to test at least a portion of a system under test.” Reply Br. 2. This argument is not commensurate with the scope of representative claim 1. Appellants’ arguments directed to the second issue assert that Jacobson does not teach test instructions to define a scan operation to be executed on logical segments representing the scan chain. Appeal Br. 14-15. Further, Appellants argue that Huisman discloses a physical segmentation of a scan chain, not logical segments. Id. at 15-16. The Examiner finds that Jacobson teaches that scan procedures on run on hardware and that the procedures are run by instructions. Answer 13. The Examiner finds that Jacobson teaches, “[t]he test procedures are integrated into a single master Scanlet which is fed logical scan chain information as disclosed in col. 20, lines 1-7. Therefore the physical scan chain configuration of Huisman would have had to have been provided logically to the master Scanlet of Jacobson for testing.” Answer 3-4. We have reviewed evidence cited by the Appeal 2013-001093 Application 12/495,336 5 Examiner and we concur with the Examiner’s findings. Accordingly, we sustain the Examiner’s rejection of representative claim 1. Appellants have not presented additional arguments with respect to the Examiner’s claims 2 through 22; accordingly, we similarly sustain the Examiner’s rejection of claims 2 through 22. DECISION The decision of the Examiner to reject claims 1 through 22 is affirmed. ORDER No time period for taking any subsequent action in connection with this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv). AFFIRMED Copy with citationCopy as parenthetical citation