Ex Parte Gong

Board of Patent Appeals and Interferences

Mar 28, 2011

10875000 (B.P.A.I. Mar. 28, 2011)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
10/875,000 06/22/2004 Zhijun Gong 15611US02 9265
23446 7590 03/29/2011
MCANDREWS HELD & MALLOY, LTD
500 WEST MADISON STREET
SUITE 3400
CHICAGO, IL 60661
EXAMINER
FARROKH, HASHEM
ART UNIT PAPER NUMBER
2188
MAIL DATE DELIVERY MODE
03/29/2011 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________

Ex parte ZHIJUN GONG
____________

Appeal 2009-008549
Application 10/875,000
Technology Center 2100
____________

Before HOWARD B. BLANKENSHIP, JAY P. LUCAS, and THU A.
DANG, Administrative Patent Judges.

BLANKENSHIP, Administrative Patent Judge.

DECISION ON APPEAL1

1 The two-month time period for filing an appeal or commencing a civil
action, as recited in 37 C.F.R. § 1.304, or for filing a request for rehearing,
as recited in 37 C.F.R. § 41.52, begins to run from the “MAIL DATE”
(paper delivery mode) or the “NOTIFICATION DATE” (electronic delivery
mode) shown on the PTOL-90A cover letter attached to this decision.

Appeal 2009-008549
Application 10/875,000

2
STATEMENT OF THE CASE
This is an appeal under 35 U.S.C. § 134(a) from the Examiner’s final
rejection of claims 1-3, 5-13, 15-23, and 25-32, which are all the claims
remaining in the application. We have jurisdiction under 35 U.S.C. § 6(b).
We reverse.

Representative Claim
1. A method for efficient execution of code in memory by a
processing device, the method comprising:

determining whether a first type of memory is present;

if said first type of memory is present, copying a loader image stored
in said first type of memory to instruction memory;

executing said copied loader image to copy application code from said
first type of memory to a second type of memory; and

executing said copied application code from said second type of
memory, wherein said instruction memory, which stores said copied loader
image, is separate from said first type of memory, which stores said loader
image and said application code, and said second type of memory.

Examiner’s Rejections
Claims 1-3, 6-8, 10-13, 16-18, 20-23, 26-28, and 30 stand rejected
under 35 U.S.C. § 103(a) as being unpatentable over Ganton (US
2003/0163656 A1) and Sih (US 2002/0138710 A1).
Claims 5, 15, and 25 stand rejected under 35 U.S.C. § 103(a) as being
unpatentable over Ganton, Sih, and Glaum (US 2005/0132179 A1).
Claims 9, 19, and 29 stand rejected under 35 U.S.C. § 103(a) as being
unpatentable over Ganton, Sih, and Vasisht (US 2004/0268116 A1).
Appeal 2009-008549
Application 10/875,000

3
Claims 31 and 32 stand rejected under 35 U.S.C. § 103(a) as being
unpatentable over Ganton, Sih, and Shida (US 2005/0015582 A1).

ISSUE
Has the Examiner shown that the combination of Ganton and Sih
teaches copying a loader image stored in a first type of memory to
instruction memory, and executing the copied loader image to copy
application code from the first type of memory to a second type of memory,
wherein the instruction memory is separate from the first type of memory
and the second type of memory, as recited in claim 1?

FINDINGS OF FACT
Ganton
1. Ganton teaches copying data, such as an operating system and a
program application, from a first memory to a second memory. Abstract;
Figs. 1-3; ¶¶ [0029] – [0031].
2. When the CPU needs data that is not already loaded into RAM,
or SDRAM, the CPU directs the serial interface controller to load the needed
data from the serial memory into RAM. ¶¶ [0029] - [0030].
Sih
3. Sih teaches an instruction decoder that decodes instructions
from an instruction memory and generates control signals that cause data to
be exchanged between various registers, data memories, and functional
units. Abstract; Fig. 2.
4. An advantage of using separate instruction memory and
instruction decode is that data buses do not have to carry instruction data,
Appeal 2009-008549
Application 10/875,000

4
therefore, the signal data may be moved and processed without interruption
from the instruction data. Thus, performance is enhanced by separating the
instruction processing from the data processing, which eliminates the need to
consume data bus cycles for instruction data movement. ¶ [0063].

PRINCIPLES OF LAW
The allocation of burdens requires that the USPTO produce the factual
basis for its rejection of an application under 35 U.S.C. §§ 102 and 103. In
re Piasecki, 745 F.2d 1468, 1472 (Fed. Cir. 1984) (citing In re Warner, 379
F.2d 1011, 1016 (CCPA 1967)). The one who bears the initial burden of
presenting a prima facie case of unpatentability is the Examiner. In re
Oetiker, 977 F.2d 1443, 1445 (Fed. Cir. 1992).

ANALYSIS
The Examiner finds that Ganton teaches copying data, such as an
operating system and a program application, from one type of memory to a
second type of memory. The Examiner also finds that the operating system
that is copied from the first type of memory to the second type of memory
contains the claimed “loader image.” Ans. 4.
The Examiner finds that Sih teaches an instruction memory that is
separate from a data memory. Ans. 5. The Examiner further finds that an
advantage of using an instruction memory that is separate from data memory
is that signal data can be moved and processed without interruption from the
instruction data. Ans. 5-6.
Ganton thus teaches copying an operating system, which may be
deemed to contain a “loader image,” from a first type of memory to a second
Appeal 2009-008549
Application 10/875,000

5
type of memory. Sih teaches a data memory that is separate from an
instruction memory. We agree with Appellant that the rejection fails to
show that either of the references, or their combination, teaches copying a
loader image stored in a first type of memory to a separate instruction
memory. Even if the combination were to be deemed to teach the claimed
copying of the loader image, we agree with Appellant there is a further
problem with the rejection.
The Examiner relies on paragraphs [0029] through [0030] of Ganton
to teach the claim 1 step of “executing said copied loader image to copy
application code from said first type of memory to a second type of
memory.” In particular, the Examiner finds that Ganton teaches that when
the CPU needs instructions or applications that are not already loaded into
RAM, the CPU directs the serial interface controller to load the needed data
from the serial memory into RAM. Ans. 4. However, the rejection fails to
establish that loading additional instructions, applications, or data from serial
memory into RAM teaches executing a loader image to copy application
code from a first type of memory to a second type of memory.
We therefore cannot sustain the § 103(a) rejection of claim 1, nor that
of dependent claims 2, 3, 5-10, 31, and 32. Because independent (base)
claims 11 and 21 are rejected on the same basis as claim 1, and each
contains limitations similar to those for which the rejection fails for claim 1,
we do not sustain the § 103(a) rejection of claims 11-13, 15-23, and 25-30.

Appeal 2009-008549
Application 10/875,000

6
CONCLUSION OF LAW
The Examiner has not shown that the combination of Ganton and Sih
teaches copying a loader image stored in a first type of memory to
instruction memory, and executing the copied loader image to copy
application code from the first type of memory to a second type of memory,
wherein the instruction memory is separate from the first type of memory
and the second type of memory, as recited in claim 1.

DECISION
The rejection of claims 1-3, 6-8, 10-13, 16-18, 20-23, 26-28, and 30
under 35 U.S.C. § 103(a) as being unpatentable over Ganton and Sih is
reversed.
The rejection of claims 5, 15, and 25 under 35 U.S.C. § 103(a) as
being unpatentable over Ganton, Sih, and Glaum is reversed.
The rejection of claims 9, 19, and 29 under 35 U.S.C. § 103(a) as
being unpatentable over Ganton, Sih, and Vasisht is reversed.
The rejection of claims 31 and 32 stand rejected under 35 U.S.C.
§ 103(a) as being unpatentable over Ganton, Sih, and Shida is reversed.

REVERSED

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