Ex Parte Gomm et al

Board of Patent Appeals and Interferences

Dec 3, 2010

11496361 (B.P.A.I. Dec. 3, 2010)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________

Ex parte TYLER J. GOMM and GARY M. JOHNSON
____________

Appeal 2009-007081
Application 11/496,361
Technology Center 2100
____________

Before JOHN A. JEFFERY, DEBRA K. STEPHENS, and JAMES R.
HUGHES, Administrative Patent Judges.

JEFFERY, Administrative Patent Judge.

DECISION ON APPEAL1
Appellants appeal under 35 U.S.C. § 134(a) from the Examiner’s
rejection of claims 10 and 13-19. Claims 1-9 have been canceled, and
dependent claims 11, 12, and 20 have been indicated as containing allowable
subject matter. See App. Br. 2. We have jurisdiction under 35 U.S.C.
§ 6(b). We affirm-in-part.

1 The two-month time period for filing an appeal or commencing a civil
action, as recited in 37 C.F.R. § 1.304, or for filing a request for rehearing,
as recited in 37 C.F.R. § 41.52, begins to run from the “MAIL DATE”
(paper delivery mode) or the “NOTIFICATION DATE” (electronic delivery
mode) shown on the PTOL-90A cover letter attached to this decision.
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2
STATEMENT OF THE CASE
Appellants invented a synchronization device and delay locked loop
(DLL) for synchronizing signals in memory devices. See generally Spec.
2-3. Claim 10 is reproduced below with the key disputed limitations
emphasized:
10. A synchronization device comprising:
a delay model circuit configured to receive a delay model input
signal and produce a delay model output signal having a time delay
with respect to the delay model input signal, wherein the delay model
is configured to model input and output delays in the synchronization
device; and
one or more tuning elements configured to provide an offset for
input/output mismatches injected by the delay model circuit.

The Examiner relies on the following as evidence of unpatentability:
Fiscus US 6,492,852 B2 Dec. 10, 2002

THE REJECTION
The Examiner rejected claims 10 and 13-19 under 35 U.S.C. § 102(b)
as anticipated by Fiscus. Ans. 3-4.2

THE CONTENTIONS
Regarding independent claims 10 and 16, the Examiner finds that
Fiscus discloses all the elements in claims 10 and 16, including the recited
tuning elements are the dividers 112 and 114. See Ans. 3-5. Appellants
argue that Fiscus’ dividers are not tuning elements because: (1) the dividers

2 Throughout this opinion, we refer to (1) the Appeal Brief filed July 7,
2008; (2) the Examiner’s Answer mailed August 5, 2008; and (3) the Reply
Brief filed October 6, 2008.
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are not “tuning elements” as defined by the Specification (App. Br. 10-11)
given their broadest reasonable construction (App. Br. 15-16); (2) an
ordinarily skilled artisan would have understood Fiscus’ dividers to divide
the input signal’s frequency, and not tune (App. Br. 12; Reply Br. 2); (3) the
dividers reduce power consumption, and do not tune (App. Br. 13, 14, 16);
and (4) the mimic circuit 104 – not the dividers 112 and 114 – is the tuning
element (App. Br. 14-15). Appellants also contend that the dividers 112 and
114 are not configured to offset mismatches injected by the delay model
circuit because divider 114 is located before the delay model circuit. App.
Br. 25-28; Reply Br. 3-4.
Appellants further assert that Fiscus fails to disclose a second tuning
element between the delay model circuit and the phase detector recited in
independent claim 16, because neither divider (e.g., 112, 114) is electrically
located between the delay model circuit and the phase detector. App. Br.
18-24; Reply Br. 4-5.
The issues before us, then, are as follows:

ISSUES
Under § 102, has the Examiner erred by finding that Fiscus discloses:
(1) a tuning element configured to provide an offset for the
input/output mismatches injected by the delay model circuit as recited in
claim 10?
(2) a second tuning element arranged between the delay model circuit
and the phase detector as recited in claim 16?

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FINDINGS OF FACT
1. Appellants have not defined a “tuning element.” See generally
Specification.
2. Fiscus discloses a DLL 100 having a “mimic” 104 and two
dividers, a dummy divider circuit 112 and a post-divider 114. The DLL 100
includes feedback for synchronizing a system clock with data output lines.
Fiscus, col. 4, l. 58 – col. 5, l. 1; col. 5, ll. 14-20; Fig. 5.
3. The mimic 104 is designed to match the delay of some “real” on-
chip delays which the DLL is to remove. Fiscus, col. 5, ll. 46-48; Fig. 5.
4. Fiscus’ dummy divider circuit 112 is placed in the reference loop
as a matching structure to the post-divider 114 present in the feedback loop.
This arrangement matches propagation delays of the dividers and prevents
unintended mismatches between the reference and feedback loops. Fiscus,
col. 5, ll. 26-30; Fig. 5.
5. The reference loop signal path begins at the divider 112’s input
signal and terminates as signal Ref-clk into phase detector 108. The
feedback loop signal path begins at post-divider 114’s input signal. Fast
Int-clk coming from the output circuit 101, passes through post-divider 114
as signal Int-clk, and exits mimic 104 as signal Fb-clk. Phase detector 108
compares the phase difference between signals Ref-clk and the Fb-clk.
Fiscus, col. 5, ll. 9-25; Fig. 5.
6. Fiscus discusses setting the mimic delay of the mimic 104 either
manually or automatically. In manual “tuning,” the mimic 104 is tuned to
match a known “real” delay. In automatic “tuning,” the mimic 104 can
contain copies of the circuits for which the DLL is to remove. Fiscus, col.
5, ll. 49-57; Fig. 5.
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7. A trim or reset 117 is located between the mimic circuit 104 and
the phase detector 108. The reset 117 forces a known initialized state at
power up conditions. Fiscus, col. 6, ll. 13-15; Fig. 6

Claims 10 and 13-15
ANALYSIS
Based on the record before us, we find no error in the Examiner’s
anticipation rejection of representative independent claim 10 which calls for,
in pertinent part, “one or more tuning elements configured to provide an
offset for input/output mismatches injected by the delay model circuit.”
Since claim 10 recites one or more tuning elements, Fiscus thus need only
disclose one tuning element configured to provide an offset for mismatches
injected by the delay model circuit to satisfy the claim’s limitations.
Contrary to Appellants’ assertions (App. Br. 9), Appellants have not
defined a “tuning element.” FF 1. Rather, Appellants merely provide
examples of how the tuning elements function in the disclosure. See App.
Br. 10-11. We therefore will not import these particular embodiments into
claim 10, such that a tuning element must correct signal deviations caused
by the delay model circuit’s sensitivities (see App. Br. 11; Reply Br. 2-3).
See Superguide Corp. v. DirecTV Enter., Inc., 358 F.3d 870, 875 (Fed. Cir.
2004). The phrase, one tuning element “configured to provide an offset for
input/output mismatches injected by the delay model circuit” includes an
element that is designed to provide some compensation for a mismatch
injected by a delay model circuit, when given its broadest reasonable
construction. See In re Am. Acad. of Sci. Tech Ctr., 367 F.3d 1359, 1364
(Fed. Cir. 2004) (internal citations and quotations omitted).
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Fiscus discloses a DLL having a mimic circuit 104 and dividers 112,
114. FF 2. The mimic circuit 104 matches real delays that the DLL is
designed to remove, and thus behaves as a delay model circuit. See FF 3.
Furthermore, dividers 112 and 114 are designed to prevent unintended
mismatches between a reference loop and a feedback loop. FF 4-5. In other
words, by preventing unintended mismatches between the reference (which
includes signal Ref-clk exiting divider 112) and feedback (which includes
signal Fb-clk exiting mimic 104) loops (see id.), both dividers 112 and 114
also assist in providing compensation for mismatches. Thus, dividers 112
and 114 do more than compensate for mismatches caused by each other.
Reply Br. 3-4. Fiscus therefore discloses tuning elements (e.g., 112, 114)
configured to provide an offset for mismatches as recited in claim 10.
Appellants contend that divider 114 is located in the DLL circuit
before the delay model circuit (e.g., 104) and thus does not provide an offset
for the mismatches injected by the delay model circuit as recited. App. Br.
25-26. While divider 114 is located prior to delay model circuit (e.g., mimic
104), Fiscus discloses another tuning element (e.g., divider 112) that
produces a signal (e.g., Ref-clk) sent to the phase detector 108. See FF 4-5.
This signal thus also assists in preventing unintended mismatches between
the reference and feedback loop. By assisting in preventing unintended
mismatches between these loops, including the feedback loop that has signal
Fb-clk exiting the delay model circuit 104 (see FF 5), Fiscus discloses a
tuning element (e.g., 112) that provides some compensation for a mismatch
injected by a delay model circuit and synchronizes data output lines. See FF
2, 4, 5. Moreover, even if both dividers 112 and 114 are needed to perform
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the recited tuning function (Reply Br. 3), divider 112 still assists in
providing compensation for mismatches injected by the delay model circuit.
Also, claim 10 recites a “tuning element configured to provide an
offset for both input and output mismatches injected by the delay model
circuit.” If the recited input mismatch injected by the model circuit includes
mismatches that were inputted into the model circuit, then as discussed
above, Fiscus further discloses divider or tuning element 114 as a tuning
element configured to provide an offset for an input mismatch (e.g., signal
Int-clk includes a mismatch) injected by the delay model circuit (e.g., mimic
104). See FF 4-5. We are therefore not persuaded that Fiscus does not
disclose a tuning element configured to provide an offset for mismatches
injected by the delay model circuit as recited in claim 10.
Appellants also assert that the mimic circuit 104—not the dividers—is
the tuning element in Fiscus. App. Br. 14-15. We disagree. First, as
explained above, divider 112 behaves as a tuning element by preventing
mismatches between the reference and feedback loops, including
compensating for mismatches injected by a delay model circuit. See FF 4-5.
Second, Fiscus’ mimic circuit 104 is designed to match (i.e., is “tuned” to)
real delays. See FF 3, 6. Third, while Fiscus discusses “tuning” in the
context of the delay model circuit (see FF 6), the mimic or model circuit 104
is not designed to provide an offset for mismatches injected by its own
circuit (e.g., 104) or the delay model circuit as recited in claim 10. See FF 3,
6.
Appellants have simply failed to provide any evidence, other than
mere assertion (App. Br. 12), that an ordinary artisan would have understood
the dividers 112 and 114 function to divide a signal’s frequency. Such
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conclusory statements unsupported by factual evidence are entitled to little
probative value. See In re Geisler, 116 F.3d 1465, 1470 (Fed. Cir. 1997).
As stated above, Fiscus’ dividers 112 and 114 function to match propagation
delays and prevent unintended mismatches between signal loops. FF 4-5.
We are therefore unpersuaded that an ordinary artisan would have
understood Fiscus’ dividers 112 and 114 to function to divide the frequency
of signals.
For the foregoing reasons, Appellants have not persuaded us of error
in the anticipation rejection of independent claim 10 based on Fiscus. We
therefore sustain the rejection of claim 10, and dependent claims 13-15
which were not separately argued (see App. Br. 9-28).

Claims 16-19
Based on the record before us, we find error in the Examiner’s
anticipation rejection of independent claim 16 which calls for, in pertinent
part, a second tuning element arranged between the delay model and the
phrase detector. Fiscus discloses that the divider or tuning element 114 is
not located between the delay model circuit 104 and the phase detector 108.
See FF 2, 4, 5. Rather, Fiscus’ divider 114 is located in the DLL between
output 101 and the mimic (i.e., delay model circuit) 104. See FF 5. In fact,
other than a trim or reset 117 (FF 7), there is no structure between the delay
model circuit and the phase detector 108. The reset 117 is also not
configured to provide an offset for mismatches injected by the delay model
circuit. See FF 7.

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The Examiner provides us with little guidance on how Fiscus is being
interpreted to include a second tuning element arranged between the delay
model circuit 104 and the phase detector 108. See Ans. 4-5. According to
the Examiner, divider 114 “is arrange[d] between 108 and 110 and [sic] 104
in figure 5.” Ans. 5. Apparently, the Examiner’s position is that the divider
114 is spatially located in Figure 5 between delay model circuit 104 and
phase detector 108. See id. However, an ordinarily skilled artisan would
have understood the phrase “arranged between the delay model circuit and
the phase detector” in the context of this disclosure to mean arranged within
the circuit and its signal path electrically between the delay model circuit
and the phase detector. See Spec. 19:9-10, 16-17; Fig. 5 (disclosing the
tuning element 74 positioned in the feedback path). The Examiner’s spatial
interpretation is therefore unreasonably broad when read in light of the
Specification and as it would be interpreted by an ordinarily skilled artisan.
See In re Suitco, 603 F.3d 1255, 1260 (Fed. Cir. 2010).
As Appellants illustrate (App. Br. 21-23), the divider 114 is arranged
before the delay model circuit 104 or is not arranged between circuit 104 and
phase detector 108. See FF 2, 5. Appellants offer an alternative
interpretation related to the signal path through the DLL. See App. Br.
23-24. However, other than signal Fb-clk, the other signal paths (e.g., Fast
Int-clk, Int-clk, Ref-clk) are not located between the delay model circuit 104
and the phase detector 108. See FF 5. And as previously stated, Fiscus has
no tuning element (e.g., 112 or 114) located in the signal path between the
delay model circuit and the phase detector. We therefore find that Fiscus
fails to disclose “a second tuning element arranged between the delay model
circuit and the phase detector” as recited in claim 16.
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For the foregoing reasons, Appellants have persuaded us of error in
the anticipation rejection of independent claim 16 based on Fiscus. We
therefore will not sustain the rejection of claim 16, and dependent claims
17-19 for similar reasons.

CONCLUSION
Under § 102, the Examiner did not err in rejecting claims 10 and
13-15, but erred in rejecting claims 16-19.

ORDER
The Examiner’s decision rejecting claims 10 and 13-19 is affirmed-in-
part.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

AFFIRMED-IN-PART

pgc

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