Ex Parte Golla

Board of Patent Appeals and Interferences

Jul 24, 2009

10880712 (B.P.A.I. Jul. 24, 2009)

UNITED STATES PATENT AND TRADEMARK OFFICE
_____________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
_____________

Ex parte ROBERT T. GOLLA
_____________

Appeal 2009-0060481
Application 10/880,712
Technology Center 2100
______________

Decided:2 July 24, 2009
_______________

Before JOHN C. MARTIN, LANCE LEONARD BARRY, and
STEPHEN C. SIU, Administrative Patent Judges.

MARTIN, Administrative Patent Judge.

DECISION ON APPEAL

1 The real party in interest is Sun Microsystems, Inc. “Appeal Brief” (Br.)
at 2.
2 The two-month time period for filing an appeal or commencing a civil
action, as recited in 37 C.F.R. § 1.304, begins to run from the decided date
shown on this page of the decision. The time period does not run from the
Mail Date (paper delivery) or Notification Date (electronic delivery).
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STATEMENT OF THE CASE
This is an appeal under 35 U.S.C. § 134(a) from the Examiner’s
rejection of claims 1, 3-14, 17, and 19-27, which are all of the pending
claims.3
We have jurisdiction under 35 U.S.C. § 6(b). We reverse.

A. Appellant’s invention
Appellant discloses various embodiments of a method and system for
sharing functional units of a multithreaded processor. Specification at
¶ 0004.
In one embodiment, each of a plurality of cores 100 (Fig. 1) may be
configured to perform fine-grained multithreading, wherein each core may
select instructions to execute from among a pool of instructions
corresponding to multiple threads such that instructions from different
threads may be scheduled to execute adjacently. Id. at ¶ 0022.
Appellant’s Figure 2 is reproduced below.

3 The “Office Action Summary” page of the Final Action incorrectly
identifies the rejected claims as claims 1-27.
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Figure 2 shows an embodiment of a core 100 that is configured to
perform fine-grained multithreading. Id. at ¶ 0023.
Instruction fetch unit 200 can be configured to provide instructions to
the rest of core 100 for execution. Id. at ¶ 0024.
Instruction pick unit 206 can be configured to select one or more
instructions to be decoded and issued to execution units 210. Id. at ¶ 0025.
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In the illustrated embodiment, the threads fetched by fetch unit 202 are
divided into two thread groups denoted TG0 and TG1. Id.
Decode unit 208 can be configured to detect and respond to
scheduling hazards not detected during operation of pick unit 206. Id. at
¶ 0027. Hazards may exist when the instructions from both thread groups
picked by pick unit 206 need to use either FGU (floating point/graphics unit)
220 or LSU (load store unit) 230 in the same cycle. Id.
Figure 4 is reproduced below.

Figure 4 is a block diagram illustrating aspects of an embodiment of
the core of Figure 2 that includes arbitration functionality. Id. at ¶ 0009.
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Specifically, decode unit 208 of Figure 4 includes hazard
detect/arbitration functionality 209, which includes arbitration indicators
410. Id. at ¶ 0048. Beginning at the left, the first arbitration indicator bit is
an FGU favor bit, FGF, for indicating which of the two thread groups can
use FGU 220 if two FGU instructions, one from each thread group, are valid
at decode. Id. at ¶ 0051. The second arbitration indicator bit is a LSU favor
bit, LSF, for indicating which of the two thread groups can use LSU 230 if
two LSU instructions, one from each thread group, are valid at decode. Id.
The third bit is a store-float favor bit, SFF, for indicating which of the two
thread groups can use both FGU 220 and LSU 230 if two store-FGU
instructions, one from each thread group, are valid at decode. Id.

B. The claims
The independent claims before us are claims 1, 17, and 27 of which
claim 1 reads:
1. A multithreaded processor, comprising:
a processor core configured to concurrently execute
instructions from a plurality of thread groups, wherein
the processor core includes:
a multithreaded instruction source configured to provide
an instruction from each of the plurality of thread
groups in a given processor core execution cycle,
wherein a given thread group comprises one or
more instructions from one or more threads;
a functional unit within the processor core and shared
between the plurality of thread groups; and
arbitration functionality configured to arbitrate between
the plurality of thread groups for access to the
functional unit;
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wherein the arbitration functionality includes a first
indicator that is associated with the functional unit
and indicates which one of the plurality of thread
groups has priority over remaining ones of the
plurality of thread groups for access to the
functional unit.
Claims App., Br. 13.

C. The references and rejection
The Examiner relies on the following references:
Alfieri US 5,745,778 Apr. 28, 1998
Kimura et al. (Kimura) US 6,105,127 Aug. 15, 2000
Claims 1, 3-14, 17, and 19-27 stand rejected under 35 U.S.C. § 103(a)
for obviousness over Alfieri in view of Kimura.
The independent claims (claims 1, 17, and 27) are argued together as a
group. Br. 4-8. We select claim 1 as representative. 37 C.F.R.
§ 41.37(c)(1)(vii).
THE ISSUE
Appellant has the burden on appeal to show reversible error by the
Examiner in maintaining the rejection. See In re Kahn, 441 F.3d 977, 985-
86 (Fed. Cir. 2006) (“On appeal to the Board, an applicant can overcome a
rejection by showing insufficient evidence of prima facie obviousness or by
rebutting the prima facie case with evidence of secondary indicia of
nonobviousness.” (citation omitted)).
The sole issue raised by Appellant’s argument regarding the rejection
of the independent claims is whether the Examiner erred in finding that the
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“first indicator” recited in the “wherein” clause of claim 1 reads on Alfieri’s
“CPU attributes.”
ALFIERI
The Examiner found that Alfieri satisfies all of the limitations of
claim 1 except that “Alfieri fails to explicitly teach concurrently executing
instructions on each core (in this case individual processors of the
multithreaded multiprocessor system)” (Answer 4), for which teaching the
Examiner relies on Kimura. Id.
Alfieri discloses a method for dynamically adjusting the affinity
between CPUs and processing threads in a multiprocessor system. Alfieri,
col. 1, ll. 9-12.
Alfieri’s Figure 1 is reproduced below.

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Figure 1 shows an overview of Alfieri’s multiprocessor data
processing system 150. Id. at col. 2, ll. 35-36.4 The Examiner reads the
recited “processor core” on one of CPUs 100 to 107 (Final Action 2) and
reads the recited “functional unit” on one of the functional units inherently
contained in the CPU. See id. (“[A] CPU inherently contains at least one
functional unit in order to function.”). Appellant is therefore incorrect to
fault the Examiner for reading the recited “functional unit” on an entire
CPU. See Reply Br. 2 (“Appellant disagrees with the Examiner that a CPU
would be considered to be a functional unit by those skilled in the art. A
CPU may have a number of functional units within it. . . . [A] CPU, as a
whole, would NOT be considered a functional unit.”).
Figure 2 of Alfieri is reproduced below.

4 Reference numeral 150 does not, however, appear in this figure.
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Figure 2 shows a diagram of a typical process 200 running on
system 150. Id. at col. 3, ll. 8-9. Process 200 contains thread groups 210,
220, and 230, of which 210, for example, is a real-time (RT) thread and was
the initial thread group in process 200. Id. at col. 3, ll. 9-11. Thread group
(TG) 210 has thread group structure (TGS) 211 and three timesharing (TS)
threads 212-214 within its thread group. Id. at col. 3, ll. 11-13.
Alfieri, under the heading “CPU Affinity” (Alfieri, col. 6, l. 20),
describes a “CPU attribute" and a “minimum allowed processing level
attribute.” Id. at col. 6, ll. 31-41. The Examiner reads the recited “first
indicator” on the CPU attribute (Answer 3), which is described as follows:
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Associated with each thread group, and available to all
CPUS in the system, are attributes specifying the thread group's
allowable CPU or set of CPUs and the thread group's minimum
allowed processing level. The CPU attribute identifies the
specific CPU or set of CPUs in the system on which the thread
group is allowed to run. Typically, this attribute will identify
all CPUs in system 150 as being allowable, though a subset of
system CPUs could be specified by the user.
Alfieri, col. 6, ll. 31-39. When viewed from the perspective of a particular
CPU, the CPU attributes thus identify the thread groups that are permitted to
access that CPU (and its functional units). The Examiner characterizes the
CPU attributes as representing “thread allowability.” See Answer 11
(“Examiner has relied on a CPU attribute indicating thread allowability (see
e.g. col. 6 lines 31-41).”).
Regarding the requirement of claim 1 that the first indicator be
“associated with the functional unit,” the Examiner found that “a functional
unit is inherently contained in a CPU, therefore the indicator associated with
the CPU is also associated with functional units in the CPU.” Id. at 10.
Regarding the further requirement of claim 1 that the first indicator
“indicate[] which one of the plurality of thread groups has priority over
remaining ones of the plurality of thread groups for access to the functional
unit” (emphasis added), the Examiner found that “[a]llowability is
reasonably applied to teach permission or the claimed ‘access’” and “[a]
thread group which is not allowed to run on a functional unit (CPU) has a
lower access priority than one which is allowed access.” Id. at 11. The
Examiner further explained that
[s]imply because Alfieri does not call the allowability of thread
group access “priority”, does not mean that it does not teach
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appellant’s claimed priority. Appellant has not claimed how a
priority decision is made, or how this affects the usage of a
functional unit. Therefore priority has been interpreted to mean
precedence over others in order, privilege, or the like.
Id. at 13.
We agree with Appellant that Alfieri’s CPU attributes do not provide
an indication of “priority,” as required by claim 1. More particularly, we are
persuaded by Appellant’s argument that
[i]n a priority scheme, it is implied that a given thread will be
selected at some point or is at least in contention for using the
resource (functional unit). . . . [T]o participate in arbitration
using some priority, the threads have to at least have access to
(i.e., be allowed to access) the CPUs. Since, the attributes
described above are used to prevent access of some thread
groups to some CPUs, the prevented thread groups cannot even
participate in the arbitration.
Reply Br. 3.
For the foregoing reasons, the rejection of independent claims 1, 17,
and 27 is reversed, as is the rejection of dependent claims 3-14 and 19-26.

DECISION
The Examiner’s decision that claims 1, 3-14, 17, and 19-27 are
unpatentable under 35 U.S.C. § 103(a) for obviousness over Alfieri in view
of Kimura is reversed.

REVERSED

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