Ex Parte Golding

Patent Trial and Appeal Board

May 24, 2016

12454153 (P.T.A.B. May. 24, 2016)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR
12/454, 153 05/13/2009 John M. Golding
57690 7590 05/27/2016
HAMILTON, BROOK, SMITH & REYNOLDS, P.C.
530 VIRGINIA ROAD
P.O. BOX 9133
CONCORD, MA 01742-9133
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
2376.2423-00l(PB09 0006) 8749
EXAMINER
TSE, YOUNG TOI
ART UNIT PAPER NUMBER
2634
NOTIFICATION DATE DELIVERY MODE
05/27/2016 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address( es):
docketing.department@hbsr.com
helpdesk@hbsr.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte JOHN M. GOLDING 1
Appeal2014-006190
Application 12/454, 153
Technology Center 2600
Before MAHSHID D. SAADAT, ST. JOHN COURTENAY III, and
KRISTEN L. DROESCH, Administrative Patent Judges.
DROESCH, Administrative Patent Judge.
DECISION ON APPEAL
1 Appellant indicates the real party-in-interest is Tellabs Operations, Inc.
Br. 2.
Appeal2014-006190
Application 12/454, 153
STATEMENT OF THE CASE
Appellant seeks review under 35 U.S.C. § 134(a) of the Examiner's
Final Rejection of claims 1, 2, 4, 8, 9, 11, 12, 14, 18, 19, and 21-26. 2,3 We
have jurisdiction under 35 U.S.C. § 6(b ).
We AFFIRM-IN-PART.
BACKGROUND
The disclosed invention relates to methods and apparatuses for
concerting a data interface format to enable data exchange between devices
operating at different clock rates. Spec. 2:8-10, Abstract
Representative claims 1 and 21, reproduced from the Claim Appendix
of the Appeal Brief, read as follows (disputed limitations in italics):
1. An apparatus for converting a data interface format to enable
data exchange between devices operating at different clock
rates, the apparatus comprising:
a clock up-converter configured to derive an up-
converted clock signal from a first clock signal at a first
clock rate of a first device and to transmit the up=converted
clock signal to a second device, the up-converted clock
signal having a phase controlled with respect to a phase of
an associated first data signal;
a clock down-converter configured to derive a down-
converted clock signal from a second clock signal at a
second clock rate of the second device and to transmit the
down-converted clock signal to the first device, the down-
converted clock signal having a phase controlled with
respect to a phase of an associated second data signal, the
2 The Examiner objects to claims 5-7, 10, 15-17, and 20 indicating these
claims would be allowable if rewritten in independent forms including the
limitations of the base claim and any intervening claims. Final Act. 9.
3 Claims 3, and 13 were cancelled previously. Response to Office Action
entered Sept. 12, 2012
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Application 12/454, 153
second clock rate being different from the first clock rate;
and
a controller configured to align the up-converted and
down-converted clock signals with the associated first and
second data signals at startup of the first and second devices
by causing the devices to transmit alignment patterns and
adjust phases of the derived up-converted and down-
converted clock signals as a function of the alignment
patterns.
21. An apparatus for converting a data interface format to enable
data exchange between devices operating at different clock
rates, the apparatus comprising:
a clock up-converter configured to derive an up-
converted clock signal from a first clock signal at a first
clock rate of a first device and to transmit the up-converted
clock signal to a second device, the up-converted clock
signal having a phase controlled with respect to a phase of
an associated first data signal;
a clock down-converter configured to derive a down-
converted clock signal from a second clock signal at a
second clock rate of the second device to transmit the down-
converted clock signal to the first device, the down-
converted clock signal having a phase controlled with
respect to a phase of an associated second data signal, the
second clock rate being different from the first clock rate;
and
a controller configured to generate control signals to
control the respective phases of the up-converted and down-
converted clock signals based on relative phases of the first
and second clock signals with respect to the associated first
and second data signals.
REJECTION
Claims 1, 2, 4, 8, 9, 11, 12, 14, 18, 19, and 21-26 stand rejected under
35 U.S.C. § 102(e) as anticipated by Zerbe (US 2009/0103572 Al;
published Apr. 23, 2009).
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ANALYSIS
We have reviewed the Examiner's rejection in light of Appellant's
arguments in the Appeal Brief presented in response to the Final Office
Action, and the arguments in the Reply Brief presented in response to the
Examiner's Answer. We agree with Appellant's arguments addressing
claims 1, 2, 4, 8, 9, 11, 12, 14, 18, and 19, but do not agree with Appellant's
arguments addressing claims 21-26. We highlight and address specific
findings and arguments for emphasis below.
Claims 1, 2, 4, 8, 9, 11, 12, 14, 18, and 19
The Examiner finds Zerbe's transmit (TX) phase controller 435 and/or
receive (RX) phase controller 413 of Figure 4 describes the following
disputed limitation of claim 1,
a controller configured to align the up-converted and down-
converted clock signals with the associated first and second
data signals at startup of the first and second devices by causing
the devices to transmit alignment patterns and adjust phases of
the derived up-converted and down-converted clock signals as a
function of the alignment patterns.
Final Act. 8-9 (citing Zerbe i-fi-120-23, 33-35); see also Ans. 5---6 (discussing
TX phase controller 435 and RX phase controller 413). The Examiner
acknowledges "that Zerbe does not use the term 'startup of the transceivers
210 and 205 by causing the transceivers to transmit alignment patterns and
between adjust phases of the derived up-converted and down-converted
clock signals as a function of the alignment patterns.'" Final Act. 5 (citing
Zerbe Figs. 2A, 3A, 4). However, the Examiner explains,
it is well known to a skilled person in the art that startup or
initialization is required in order to synchronize the re-time
serial data TXDl and the transmission clock TxClkl controlled
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Application 12/454, 153
by the transmission phase adjuster 220 or the transmission
phase controller 435 prior [to] the transmission of the time
serial data TXD 1 from the transceiver 205 to the transceiver
210.
Id.; see Zerbe Fig. 2A. The Examiner further asserts "the transmission data
TX 1 is the same as the alignment pattern recited in the claims." Final Act.
5; see Zerbe Fig. 2A. On the foregoing bases, the Examiner explains,
the clock Synthesizer 247 and the phase adjuster 220 of figures
2A and 3A or the PLL 409 and the TX phase controller 435 of
figure 4 perform the alignment of the down-converted clock
signal TxClkl with the associated second data signal TXDl at
startup or initialization of the transceiver 205 by causing the
transceiver to transmit the transmission data TX 1 and adjust the
phase of the derived down-converted clock signal TxClkl as a
function of the transmission data TX 1.
Final Act. 5 (citing Zerbe i1i120, 34, 35).
Appellant argues Zerbe does not describe the disputed limitation of
claim 1. Br. 6. Specifically, Appellant contends Zerbe's TX phase
controller 435 and RX phase controller 413 do not cause any device to
transmit alignment patterns, nor cause any device to adjust phases of clock
signals as a function of alignment patterns. Id. at 7; see id. at 9. Appellant
further asserts the alignment pattern recited in claim 1 is distinct from
Zerbe' s transmit data TX 1 data because TX 1 is not transmitted by either of
the receivers 205, 210 shown in Fig. 2A. Id. at 9. Appellant further argues
TXl data is not received by any control circuitry or the phase controller 435
so it cannot be used as a basis for adjusting the clock signal TxClkl. Id.
We agree with Appellant's arguments that, contrary to the Examiner's
findings, Zerbe does not describe transmitting the transmission data TX 1 or
receipt of the transmission data TX 1 at phase adjuster 220 or TX phase
controller 435. Instead Zerbe describes transmitter 218 of transceiver 205
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Application 12/454, 153
receives transmit data TX 1 on a first data input terminal, synchronizes TX 1
to a first clock TxClkl and conveys the re-timed serial data TXDl to
transceiver 210 via channel 212. Zerbe i-f 20, Fig. 2A.
Appellant further argues Zerbe fails to even mention the use of an
"alignment pattern." Br. 7. In response, the Examiner acknowledges that
Zerbe does not use the phrase "'alignment patterns,"' but asserts,
the waveform diagrams shown in FIG. 2B and FIG. 2C each
illustrates the transmission data TXDM 216, which corresponds to the
associated first data signal including patterns 264 in the time interval
and the transmission data TXDN 215, which corresponds to the
associated second data signal including patterns 262 in the same time
interval aligned with the patterns 264, wherein the transmission data
TXD M 216 is transmitted by the transmitter 23 5 within the first
transceiver 210 and the transmission data TXDN 216 is transmitted by
the transmitter 223 within the second transceiver 205.
Ans. 7-8 (citing Zerbe i-fi-1 25-26).
The Examiner does not direct us to a sufficient factual finding to
demonstrate that Zerbe describes elements 262 and 264 depicted in Figures
2B and 2C correspond to alignment patterns. Furthermore, the Examiner
does not direct us to a sufficient factual basis to demonstrate that Zerbe
discloses a controller that causes the first and second devices to transmit
elements 262, 264 depicted in Figures 2B and 2C, and adjust phases of the
clock signals as a function of elements 262, 264 depicted in Figures 2B and
2C. Instead, Zerbe discloses that the rising and falling edges of data symbol
255 of TXDl on channel 212 induces far end cross talk (FEXT) and near
end cross talk (NEXT) artifacts 262 and 264 in nearby channels 215 and
216. Zerbe i-fi-124, 25, Fig. 2C. Zerbe further discloses that the phase-adjust
circuits 220 and 225 can alter the transmit timing of data symbol 255 of
TXD 1 on channel 212 with respect to the data on channels 215 and 216 to
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Application 12/454, 153
reduce the impact of the crosstalk. Zerbe if 26. The FEXT and NEXT
artifacts 262 and 264 can be offset with respect to sampling instants of the
received data to instants at which channels 215, 216 are less sensitive to
crosstalk. See Zerbe if 26, Fig. 2B. For at least these reasons, we are
constrained to reverse the Examiner's rejection of claims 1, 2, 4, 8, 9, 11, 12,
14, 18, and 19 as anticipated by Zerbe.
Claims 21-26
Appellant contends "[i]ndependent claims [] 21 and 24 include
elements similar to the features described above with respect to claim 1."
Br. 9. Appellant asserts that for reasons similar to those reasons addressing
claim 1, Zerbe fails to disclose "a controller configured to generate control
signals to control the respective phases of the up-converted and down-
converted clock signals based on relative phases of the first and second
clock signals with respect to the associated first and second data signals," as
recited in claim 21, and "generating control signals to control the respective
phases of the up-converted and down-converted clock signals based on
relative phases of the first and second clock signals with respect to the
associated first and second data signals," as recited in claim 24. Id. at 9-10.
Appellant's arguments addressing claim 1 do not address sufficiently
the disputed limitations of claims 21 and 24 because claims 21 and 24 are of
different scope than, and do not include the disputed limitations of, claim 1.
For example, claims 21 and 24 do not recite alignment patterns, transmitting
alignment patterns, and adjusting phases of the clock signals as a function of
the alignment patterns. Thus, Appellant's arguments addressing the
deficiencies of Zerbe with respect to the disputed limitations of claim 1 are
not germane to claims 21 and 24. Appellant does not otherwise
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Application 12/454, 153
substantively address the Examiner's finding that Zerbe describes the clock
synthesizer 247 and the phase adjuster 220 of Figures 2A and 3A or the
phase-lock loop (PLL) 409 and the TX phase controller 435 of Figure 4
performing the generation of control signals to control the respective phases
of the up-converted and down-converted clock signals TxClkM and TxClkl
based on relative phases of the first and second clock signals LRC2 and
LRCl with respect to the associated first and second data signals TXDM and
TXDI. See Final Act. 6; Br. 6-10. Accordingly, we are not persuaded of
error in the rejection of claims 21, 24 and claims 22, 23, 25, and 26
dependent therefrom.
DECISION
We REVERSE the rejection of claims 1, 2, 4, 8, 9, 11, 12, 14, 18, and
19 under 35 U.S.C. § 102(e) as anticipated by Zerbe.
We AFFIRM the rejection of claims 21-26 under 35 U.S.C. § 102(e)
as anticipated by Zerbe.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(l )(iv).
AFFIRMED-IN-PART
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