Ex Parte Gissel et al

Patent Trial and Appeal Board

May 19, 2017

13159119 (P.T.A.B. May. 19, 2017)

United States Patent and Trademark Office
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
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Alexandria, Virginia 22313-1450
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APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
13/159,119 06/13/2011 Thomas R. Gissel 0464-009/YOR920110358US1 1823
55459 7590 05/23/2017
PATENT PORTFOLIO BUILDERS, PLLC
P.O. BOX 7999
Fredericksburg, VA 22404
EXAMINER
TSAI, SHENG JEN
ART UNIT PAPER NUMBER
2136
NOTIFICATION DATE DELIVERY MODE
05/23/2017 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
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PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte THOMAS R. GISSEL, AVRAHAM LEFF,
BENJAMIN MICHAEL PAREES, and JAMES THOMAS RAYFIELD
Appeal 2016-004971
Application 13/159,119
Technology Center 2100
Before JOHN A. JEFFERY, MATTHEW J. McNEILL, and STEVEN M.
AMUNDSON, Administrative Patent Judges.
JEFFERY, Administrative Patent Judge.
DECISION ON APPEAL
Appellants appeal under 35 U.S.C. § 134(a) from the Examiner’s
decision to reject claims 1—10 and 12—24. We have jurisdiction under 35
U.S.C. § 6(b). We affirm.
STATEMENT OF THE CASE
Appellants’ invention caches data in fast and slow access memory
portions. The fast access memory portion includes pointers to locations in
the slower access memory portions containing associated bulk data. In one
aspect, the bulk data is modified asynchronously with (a) receiving an
associated request to modify the data, and (b) confirming that the
modification is complete so that an associated application continues running
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Application 13/159,119
before the bulk data is modified. See generally Abstract; Spec. Tflf 30, 34.
Claim 1 is illustrative:
1. A method for caching data, the method comprising:
maintaining a cache within a computing system, the cache comprising
a fast access memory portion and a slow access memory portion;
storing a plurality of data sets in the fast access memory portion of the
cache, each data set comprising key data and bulk data;
identifying a given data set from the plurality of data sets stored in the
fast access memory portion to be moved to the slow access memory portion;
moving only the bulk data of the identified given data set to the slow
access memory portion;
creating a pointer to a memory location within the slow access
memory portion containing the bulk data of the identified given data set;
associating the pointer with the key data of the identified given data
set;
storing the pointer in the fast access memory portion;
receiving instructions from an application associated with the
identified given data set for modification of the identified data set;
providing the application with confirmation of completion of the
modification; and
modifying the bulk data of the identified given data set in the slow
access memory portion in accordance with the received instructions;
wherein actual modification of the bulk data in the step of modifying
the bulk data in the slow access memory portion occurs asynchronously with
the steps of receiving the request and providing the application with
confirmation so that the application does not wait and continues running
before the actual modification of the bulk data as if the actual modification
of bulk data has been completed.
THE REJECTIONS
The Examiner rejected claims 1—3, 5—8, 10, 12—18, 20-22, and 24
under 35 U.S.C. § 103(a) as unpatentable over Caulkins (US 2011/0191523
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Application 13/159,119
Al; Aug. 4, 2011), Armangau (US 2006/0294164 Al; Dec. 28, 2006), and
Son (US 7,076,605 Bl; July 11, 2006). Final Act. A-22.1
The Examiner rejected claim 4 under 35 U.S.C. § 103(a) as
unpatentable over Caulkins, Armangau, Son, and Szonye (US 2008/0270687
Al; Oct. 30, 2008). Final Act. 22.
The Examiner rejected claims 9, 19, and 23 under 35 U.S.C. § 103(a)
as unpatentable over Caulkins, Armangau, Son, and Schroeder (US
2012/0254579 Al; Oct 4, 2012). Final Act. 23-24.
THE REJECTION OVER CAULKINS, ARMANGAU, AND SON
The Examiner finds that Caulkins discloses, among other things,
maintaining a cache comprising (1) a fast access memory portion (volatile
memory 201), and (2) a slow access memory portion, namely the flash
memories 202, 203 and “other” memory 204 in Figure 2. Final Act. 4—8.
According to the Examiner, Caulkins discloses every recited element of
claim 1 except for (1) moving only bulk data to the slow access memory
portion, and (2) the actual modification of bulk data in the slow access
memory portion occurs asynchronously with (a) receiving the recited
request, and (b) providing an application with confirmation that the
modification was completed so that the application does not wait and
continues running before the actual modification. Final Act. 8—13; Ans. 4—8.
The Examiner, however, cites Armangau and Son for teaching limitations
1 Throughout this opinion, we refer to (1) the Final Rejection mailed May
22, 2015 (“Final Act.”); (2) the Appeal Brief filed October 26, 2015 (“App
Br.”); (3) the Examiner’s Answer mailed February 12, 2016 (“Ans.”); and
(4) the Reply Brief filed April 11, 2016 (“Reply Br.”).
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(1) and (2), respectively, in concluding that the claim would have been
obvious. Id.
Appellants argue that Caulkins and Armangau do not teach or suggest
asynchronously handling data modifications in a slow and fast cache, let
alone provide a reason for modifying their disclosures to do so as the
Examiner proposes. App. Br. 5—10; Reply Br. 2-4. Appellants add that Son
teaches away from the claimed invention providing notification that data
was written to disk after flush criteria are met. App. Br. 9—10; Reply Br. 2—
4.
ISSUES
(1) Under § 103(a), has the Examiner erred in rejecting claim 1 by
finding that Caulkins, Armangau, and Son collectively would have taught or
suggested actual modification of bulk data in the slow access memory
portion occurs asynchronously with (a) receiving the recited request, and (b)
providing an application with confirmation that the modification was
completed so that the application does not wait and continues running before
the actual modification (“the asynchronous modification limitation”)?
(2) Is the Examiner’s proposed combination supported by articulated
reasoning with some rational underpinning to justify the Examiner’s
obviousness conclusion? This issue turns on whether Son teaches away
from the claimed invention.
ANALYSIS
As noted above, the Examiner relies principally on Caulkins for
teaching every recited element of claim 1 except for (1) moving only bulk
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data to the slow access memory portion, and (2) the asynchronous
modification limitation. Ans. 4—5. Regarding the first difference, the
Examiner acknowledges that although Caulkins moves both bulk and key
data from faster to slower memory, the Examiner nonetheless concludes that
moving only bulk data to a slow access memory portion as claimed would
have been obvious in light of Armangau. Ans. 4; Final Act. 9—10.
Despite Appellants’ arguments to the contrary (App. Br. 7—8; Reply
Br. 2), we see no error in the Examiner’s reliance on Armangau merely for
this limited purpose. Appellants’ contentions regarding Armangau’s alleged
shortcomings pertaining to the asynchronous modification limitation are
inapposite, for they are not germane to the limited purpose for which
Armangau was cited. Appellants’ arguments regarding (1) Caulkins’ alleged
shortcomings pertaining to the asynchronous modification limitation, and (2)
Son’s alleged shortcomings regarding using pointers with key data (App. Br.
6, 8) are likewise unavailing for, here again, these references were not cited
for teaching those limitations. See Ans. 4-5. In short, Appellants’
arguments regarding Caulkins’ and Armangau’s individual shortcomings do
not show non-obviousness where, as here, the rejection is based on the cited
references’ collective teachings. See In re Merck & Co., Inc., 800 F.2d
1091, 1097 (Fed. Cir. 1986).
Nor do we find error in the Examiner’s reliance on Son’s Background
section for at least suggesting the asynchronous modification limitation.
Ans. 5—6 (citing Son, col. 1,11. 22—34). That section explains that, to
improve throughput, most of the then-current disk drives included a write
cache that, when enabled, enabled a controller to (1) write data blocks
directly to that cache; (2) thereafter indicate to a data source that the data
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was written to disk; and (3) transfer the data from the write cache to the disk
at a later time. Son, col. 1,11. 22—34.
Given this functionality, we see no error in the Examiner’s finding
that event (1) noted above involves receiving a request to modify bulk data;
event (2) represents providing confirmation to the source application; and
event (3) represents actually modifying the bulk data. Ans. 6—7. Nor do we
see error in the Examiner’s finding that because event (3), namely actual
modification of bulk data, occurs after events (1) and (2) at some unspecified
later time, this modification occurs asynchronously with events (1) and (2).
Id. We reach this conclusion even under Appellants’ own construction of
the term “asynchronously” (i.e., at different times). See App. Br. 7
(articulating this construction).
To be sure, despite improving throughput, Son’s write-cache-based
technique risks losing data if, for example, power is lost before flushing the
write cache. Son, col. 1,11. 35—39. Therefore, in mission-critical and
enterprise applications generally, the controller writes a data block from the
source to the write cache, and flushes the block write from that cache by
issuing a flush command causing the cache to be written or flushed to the
disk. Id., col. 1,11. 40-45. Moreover, one aspect of Son’s invention sends a
message to a data source indicating that blocks of data were written to a disk
upon satisfying certain flush criteria as Appellants indicate. App. Br. 8
(citing Son, col. 1,1. 60 —col. 2,1. 3).
But despite these additional approaches and Appellants’ arguments to
the contrary (App. Br. 7—9; Reply Br. 3—4), Son does not teach away from
the claimed invention. First, Son’s write-cache-based technique in the
Background section improves throughput—a performance-enhancing
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technique used in most disk drives manufactured at that time. See Son, col.
1,11. 22—24. Although there is a risk of losing data if, for example, power is
lost before flushing the write cache {id., col. 1,11. 35—39), this risk does not
mean that data will necessarily be lost: only a risk of loss exists under these
circumstances. Depending on the application, skilled artisans may be
willing to accept such a risk to realize the benefits of Son’s write-cache-
based technique, namely improved throughput, as was apparently the case
with most disk drives manufactured at the time of Son’s invention. See Son,
col. 1,11. 22 40. In short, weighing such countervailing factors amounts to
an engineering trade-off well within the level of ordinarily skilled artisans.
Although Son describes an approach that mitigates the risk of losing
data noted in the Background section, this approach is described only in
connection with mission-critical and enterprise applications generally—not
all applications. See Son, col. 1,11. 40-45. So even assuming, without
deciding, that the write-cache-based approach in Son’s Background section
relied upon by the Examiner is somehow inferior to, or less desirable than,
Son’s other approaches at least with respect to risking data loss in mission-
critical and enterprise applications, that alone is insufficient to teach away
from the ostensibly inferior alternative unless the disclosure criticizes,
discredits, or otherwise discourages that alternative—which it does not. See
In re Fulton, 391 F.3d 1195, 1200-01 (Fed. Cir. 2004). That Son may prefer
other approaches for mission-critical or enterprise applications does not
mean that Son discredits or discourages the relied-upon write-cache-based
alternative for other applications. To the contrary, the fact that the majority
of disk drive manufacturers employed such a technique at that time—despite
the risk of data loss—only further underscores the viability of that
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alternative. That this alternative entails a risk of data loss may well be
outweighed by its improved throughput advantages in certain applications—
an engineering trade-off as noted previously.
Therefore, Son does not teach away from the claimed invention.
Rather, the Examiner’s proposed combination uses prior art elements
predictably according to their established functions—an obvious
improvement. See KSR Int’l Co. v. Teleflex, Inc., 550 U.S. 398, 417 (2007).
On this record, then, the Examiner’s proposed combination is supported by
articulated reasoning with some rational underpinning to justify the
Examiner’s obviousness conclusion.
Therefore, we are not persuaded that the Examiner erred in rejecting
claim 1, and claims 2, 3, 5—8, 10, 12—18, 20—22, and 24 not argued
separately with particularity.2
THE OTHER OBVIOUSNESS REJECTIONS
We also sustain the Examiner’s obviousness rejections of claims 4, 9,
19, and 23. Final Act. 22—24. Appellants reiterate similar arguments made
in connection with claim 1, and allege that the additional cited references fail
to cure those purported deficiencies. See App. Br. 10. We are not persuaded
by these arguments for the reasons previously discussed.
2 Although no antecedent basis exists for “the request” in claim 1, we leave
the question of whether this inconsistency renders the claim indefinite to the
Examiner to consider after this opinion.
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CONCLUSION
The Examiner did not err in rejecting claims 1—10 and 12—24 under
§ 103(a).
DECISION
The Examiner’s decision rejecting claims 1—10 and 12—24 is affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(l)(iv).
AFFIRMED
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