Ex Parte Giles et al

Patent Trial and Appeal Board

Jun 28, 2013

11588903 (P.T.A.B. Jun. 28, 2013)

UNITED STATES PATENT AND TRADEMARK OFFICE
_____________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
_____________

Ex parte CHRIS M. GILES, BRYAN HORNUNG, MICHAEL
J. PHELPS, and JOSEPH F. ORTH
____________________

Appeal 2011-000590
Application 11/588,903
Technology Center 2100
____________________

Before: TREVOR M. JEFFERSON, MICHAEL J. STRAUSS, and LYNNE
E. PETTIGREW, Administrative Patent Judges.

JEFFERSON, Administrative Patent Judge.

DECISION ON APPEAL

Appeal 2011-000590
Application 11/588,903

2
STATEMENT OF CASE1
Appellants appeal under 35 U.S.C. § 134 from a rejection of claims 1-
20.2 We have jurisdiction under 35 U.S.C. § 6(b).
We affirm-in-part.
Introduction
The claims are directed to address handling by assigning values to two
or more address spaces with address fields of different lengths. Spec. page
3. Claims 1 and 8, reproduced below with disputed limitations in italics, are
illustrative of the claimed subject matter:
1. A method of assigning addresses in two or more address
spaces with address fields of different lengths, comprising:
defining address types;
assigning a value to first bits at the high ends of the
address fields to identify a first said address type;
assigning second bits at the low ends of the address fields
to identify addresses of the first said address type; and
inserting different numbers of additional bits between the
first bits and the second bits in the two or more address spaces.

8. A method of interpreting an address, comprising:
determining a value for an address length;
reading type bits from a high end until an address type is
recognized;
reading from the address further bits the number and position of
which is determined by the address type and the address length; and
for an address of at least one address type and at least one
address length, ignoring one or more bits between the type bits and
the further bits.

1 Throughout the decision, we refer to the Appellants’ Appeal Brief (“App.
Br.,” filed Apr. 19, 2010), and Reply Brief (“Reply Br.,” filed Sep. 13,
2010), and the Examiner’s Answer (“Ans.,” mailed Jul. 12, 2010).
2 The Real Party in Interest is Hewlett-Packard Development Company, L.P.
Appeal 2011-000590
Application 11/588,903

3

Rejections
The Examiner made the following rejections:
Claims 1-20 stand rejected under 35 U.S.C §103(a) as being
unpatentable over Prakash (US 2007/0286152 A1, Dec. 13, 2007) and
Strongin (US 6,559,850, May 6, 2003). Ans. 3-5.

OPINION
Independent Claim 1 – 35 U.S.C §103(a)
Appellants argue that Prakash and Strongin fail to teach or suggest
inserting additional bits between the high order address type bits and low
order address bits as recited in independent claim 1. App. Br. 14, 16.
Appellants contend that the Examiner improperly relies on inherency to
support that Prakash and Strongin teach or suggest inserting any additional
bits between bits identifying an address type and bits identifying an address.
App. Br. 14 (citing Prakash ¶ [0138], Fig. 5). Appellants further contend
that Strongin is not properly combinable with Prakash because it is directed
toward memory access request using accelerated graphics protocol that
breaks the access request into three separate 8-bit parts: low order address
bits, mid-order address and command bits and high order address bits. App.
Br. 16. Appellants argue that the mid-order command bits taught in
Strongin are not applicable to and used by the communication in Prakash.
App. Br. 17.
The Examiner answers that Prakash, which is directed towards
providing communications using shorter addresses between multiple nodes
via airlink, teaches an address containing an address type bit and a variable
Appeal 2011-000590
Application 11/588,903

4
length address that may include 0 up to a maximum predetermined number
of bits. Ans. 7 (citing Prakash, ¶[0138], Fig. 5). The Examiner also found
that Prakash teaches including destination/source address information. Id.
(citing Prakash, ¶¶ [0108]-[0116]). With respect to Strongin, the Examiner
found that it teaches or suggests mid-order address bits or commands and
high order address bits in its addressing scheme. Id. (citing Strongin, col 11,
ll. 36-42). The Examiner noted that one of ordinary skill in the art would
have recognized the benefits of including command structure of Strongin
into the basic addressing and communication with external devices taught in
Prakash and Strongin because the combination would allow a system to not
only address the destination node, but also add functionality. Id (citing
Strongin, col 11, ll. 36-42).
Having reviewed Appellants’ arguments, we agree with the Examiner.
The Examiner found, and we agree, that Prakash teaches or suggests “an
address structure of high order bits that define a plurality of address types”
and lower order address bits (Ans. 8; see Prakash, ¶¶ [008], [0138], Fig. 5).
We also agree with the Examiner that Appellants’ Specification shows
higher order and lower order bits with intervening 0 bits having no function
inserted between the address type high order bits and the address in the
lower order bits. Spec., ¶¶ [0028]-[0030], Table 3; see Ans. 6 (discussing
same). The addressing scheme shown in Prakash includes the lower order
and higher order bits as disclosed in claim 1 and Appellants’ Specification.
See Prakash, Fig. 5, Table 3. We do not agree with Appellants’ argument
the Examiner is relying on inherency with respect to arbitrary assignment of
additional bits in Prakash and Strongin. App. Br .14-15. Instead, we agree
with the Examiner’s findings that Prakash and Strongin teach or suggest that
Appeal 2011-000590
Application 11/588,903

5
the address can be a variable length address that may include 0 up to a
predetermined number of bits. Ans. 7 (citing Prakash, ¶[0138], Fig. 5).
We are also not persuaded by Appellants’ arguments that the
command bits in the mid-order portion of Strongin have no place in the
method of Prakash and would change the principle of operation of Prakash.
See App. Br. 17. The Examiner offered a articulated reasoning with rational
underpinning for the combination of the command and addressing of
Strongin into the communication system of Prakash to allow addressing of
destination nodes and coupling a command structure to the system. See Ans.
7. Contrary to Appellants’ arguments, forming the combination of Strongin
and Prakash does not require slavishly incorporating the entirety of the
encoding scheme of Strongin. Reply 4. “A person of ordinary skill is also a
person of ordinary creativity, not an automaton.” KSR Int’l Co. v. Teleflex
Inc., 550 U.S. 398, 421 (2007). As the Examiner asserts, both Prakash and
Strongin relate to addressing and communicating with external devices via
addressing means. See Ans. 7.
Based on the foregoing, the Examiner did not err in finding that
Prakash and Strongin teach or suggest inserting additional bits between the
high order address type bits and low order address bits as recited in
independent claim 1. Because Appellants do not argue the dependent claims
separately (see App. Br. 13, 16-18), we sustain the Examiner’s rejection of
independent claim 1 and dependent claims 2-7 under 35 U.S.C §103(a).

Independent Claims 8 and 10 – 35 U.S.C §103(a)
Appellants argue that Prakash and Strongin fail to teach or suggest
“ignoring one or more bits between the type bits and the further bits” as
Appeal 2011-000590
Application 11/588,903

6
recited in claim 8 and “ignor[ing] one or more additional bits between the
first bits and the second bits for an address of at least one address type and at
least one address length” as recited claim 10. App. Br. 18-21. Specifically,
Appellants contend that the Examiner improperly relies on the “obvious to
try” rationale (App. Br. 15) to support that the middle bits in the
combination of Prakash and Strongin are ignored because they fail to “make
any provision for ignoring any bits of their address” (App. Br. 19, 20).
The Examiner answers that the combination of Prakash and Strongin
“teaches an address structure of high order bits defining plurality of address
types (Prakash), mid-order command bits (Strongin) and low order address
bits (Prakash & Strongin) wherein on repeated requests the high-order and
mid-order bits … are only transmitted if they have changed since the
previous request.” Ans. 8 (citing Strongin, col. 11, ll. 36-42). Given these
parameters, the Examiner found that Strongin suggests that the mid-order
and high order bits are ignored by the receiving unit as shown in the
transaction id generation process. Id. (citing Strongin, col. 11, l. 48 – col.
12, l. 28).
We are not persuaded by the Examiner’s argument that “the receiving
unit [in Strongin] by retaining the original high order and mid-order address
bits (granted that they remain unchanged), would provide an inherent
functionality of ignoring the said bits associated with the transaction [id].”
Ans. 8. The transaction id generation process disclosed in Strongin does not
send the additional bits and therefore does not disclose ignoring bits between
the high end address type bits and the further bits as recited in claims 8 and
10. See Reply Br. 6.
Appeal 2011-000590
Application 11/588,903

7
Based on the foregoing, we find that the Examiner erred in finding
that the combination of Prakash and Strongin teaches or suggests “ignoring
one or more bits between the type bits and the further bits” as recited in
claim 8 and “ignor[ing] one or more additional bits between the first bits and
the second bits for an address of at least one address type and at least one
address length” as recited claim 10. Accordingly, we do not sustain the
Examiner’s rejection of independent claims 8 and 10 and their associated
dependent claims 9 and 11-20 under 35 U.S.C. §103(a). We need not reach
Appellants’ remaining arguments with respect to these claims. See App. Br.
18-21.

DECISION
For the above reasons, the Examiner’s rejection of claims 1-7 is
AFFRIRMED and the Examiner’s rejection of claims 8-20 is REVERSED.

AFFIRMED-IN-PART

msc