Ex Parte Ghai et al

Patent Trials and Appeals Board

May 30, 2019

12424284 - (D) (P.T.A.B. May. 30, 2019)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR
12/424,284 04/15/2009 Sanjeev Ghai
50170 7590 05/31/2019
IBM CORP. (WIP)
c/o WALDER INTELLECTUAL PROPERTY LAW, P.C.
1701 N. COLLINS BL VD.
SUITE 2100
RICHARDSON, TX 75080
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
AUS920080798US 1 1268
EXAMINER
LOONAN, ERIC T
ART UNIT PAPER NUMBER
2131
MAIL DATE DELIVERY MODE
05/31/2019 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte SANJEEV GHAI, GUY LYNN GUTHRIE, STEPHEN
POWELL, and WILLIAM JOHN STARKE
Appeal2017-008279
Application 12/424,284 1
Technology Center 2100
Before JOHNNY A. KUMAR, CATHERINE SHIANG, and
NORMAN H. BEAMER, Administrative Patent Judges.
SHIANG, Administrative Patent Judge.
DECISION ON APPEAL
Appellants appeal under 35 U.S.C. § 134(a) from the
Examiner's rejection of claims 1, 6, 11, 16, and21-36. We have
jurisdiction under 35 U.S.C. § 6(b).
We reverse.
1 Appellants identify International Business Machines Corporation as
the real party in interest. App. Br. 2.
Appeal2017-008279
Application 12/424,284
STATEMENT OF THE CASE
Introduction
The present invention relates to "information handling systems
(IHSs), and more specifically, to cache memory systems that IHSs
employ." Spec. ,r 1. Claim 1 is exemplary:
1. A method, implemented within a chiplet of a
processor integrated circuit, comprising:
requesting, by a processor element of the chip let,
access to a cache memory to conduct operations in the
cache memory, the operations including load operations
and store operations;
interrupting, by control logic of the chip let, a store
operation in progress in the cache memory when the
processor element sends a load operation to the cache
memory;
performing, by the cache memory of the chip let,
the load operation; and
scheduling, by the control logic of the chip let, the
store operation for access to the cache memory to
conduct a remainder of the store operation after the load
operation completes, wherein the chiplet comprises:
cache arbiter logic that is configured to schedule
access operations for accessing the cache memory;
directory arbiter logic, coupled to the cache arbiter
logic, that is configured to access a directory that stores
address and state information for cache lines in the cache
memory;
core interface unit control logic, coupled to the
cache arbiter logic and directory arbiter logic, that is
configured to receive load requests from a core load
request bus associated with the processor element; and
store queue control logic, coupled to the cache
arbiter logic, the directory arbiter logic, and the core
interface unit control logic, that is configured to receive
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Application 12/424,284
store requests from a core store bus associated with the
processor element, and wherein:
the core interface unit control logic and the
directory arbiter logic perform a first set of first stage
arbitration operations,
the cache arbiter logic and the store queue control
logic perform a second set of first stage arbitration
operations,
results of the second set of first stage arbitration
operations are provided to second stage arbitration logic,
and
interrupting the store operation in progress in the cache
memory when the processor element sends a load operation to
the cache memory comprises sending results of the first set of
first stage arbitration operations directly to third stage
arbitration logic thereby bypassing the second stage arbitration
logic.
References and Re} ections2
Claims 1, 6, 11, 16, and 21-36 stand rejected under pre-AIA 35
U.S.C. § 112, first paragraph, as failing to comply with the written
description requirement. Final Act. 3--4.
Claims 1, 6, 11, 16, and 21-36 stand rejected under pre-AIA 35
U.S.C. § I03(a) as being unpatentable over the collective teachings of
Herbst (US 6,907,499 B2, issued June 14, 2005), Yuan (US 7,184,341
B2, issued Feb. 27, 2007), Guthrie (US 2006/0184743 Al, published
Aug. 17, 2006), and Applicant Admitted Prior Art (AAP A). Final
Act. 5-20.
2 Throughout this opinion, we refer to the ( 1) Final Office Action
dated July 27, 2017 ("Final Act."); (2) Appeal Brief dated November
29, 2016 ("App. Br."); (3) Examiner's Answer dated March 23, 2017
("Ans."); and (4) Reply Brief dated May 11, 2017 ("Reply Br.").
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Appeal2017-008279
Application 12/424,284
ANALYSIS
Pre-AJA 35 U.S.C. § 112,firstparagraph
The Examiner determines claims 1, 6, 11, 16, and 21-36 fail to
comply with the written description requirement with respect to the
following claim limitations: (i) "cache arbiter logic" and "directory
arbiter logic," as recited in each of independent claims 1, 6, 11, and
16; (ii) "sequencer logic," as recited in each of dependent claims 24,
28, 32, and 36; and (iii) "select a load request ... for immediate
access to the directory ahead of any requests selected by the store
queue control logic, the cache arbiter logic, or the directory arbiter
logic," as recited in each of dependent claims 21, 25, 29 and 33. See
Final Act. 3--4; Ans. 2-5.
To satisfy the written description requirement, the disclosure
must reasonably convey to skilled artisans that Appellants possessed
the claimed invention as of the filing date. See Ariad Pharms., Inc. v.
Eli Lilly & Co., 598 F.3d 1336, 1351 (Fed. Cir. 2010) (en bane).
Specifically, the description must "clearly allow persons of ordinary
skill in the art to recognize that [the inventor] invented what is
claimed" and
the test requires an objective inquiry into the four comers
of the specification from the perspective of a person of
ordinary skill in the art. Based on that inquiry, the
specification must describe an invention understandable
to that skilled artisan and show that the inventor actually
invented the invention claimed.
Id. (internal quotations and citations omitted).
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Application 12/424,284
For (i) and (ii), Appellants cite paragraphs 48-57 and 78, and
Figures 4 and 5A of the Specification for supporting the claim
limitations "cache arbiter logic," "directory arbiter logic," and
"sequencer logic." See App. Br. 7-9; Reply Br. 2-7. We agree with
Appellants that one skilled in the art would understand Figure 4 shows
a cache arbiter logic 420 "that schedules reads and writes in the L2
cache memory 309 ," and a directory arbiter logic 421 "that controls
access to the CPU/snoop directory (CPU/SNP DIR) 491 "; and Figure
5A shows a sequencer logic 528 "that controls the sequence of
operations that the L2 cache system feeds to the L2 cache memory for
execution." Spec. ,r,r 49, 78; Figs. 4, 5A. Therefore, the
"specification describe[ s] an invention understandable to that skilled
artisan and show[ s] that the inventor actually invented the invention
claimed" with respect to the claim limitations "cache arbiter logic,"
"directory arbiter logic," and "sequencer logic." Ariad Pharms., 598
F.3dat 1351.
For (iii), Appellants cite paragraph 66 and Figures 4 and 5A of
the Specification for supporting the claim limitation "select a load
request ... for immediate access to the directory ahead of any
requests selected by the store queue control logic, the cache arbiter
logic, or the directory arbiter logic." See App. Br. 9-11; Reply Br. 7-
9. Appellants argue, and we agree:
[P]aragraph [0066] of the present specification describes
immediate access to the directory and specifically states
that "the winner of the 3 way arbitration (ARB3) at 529
receives access to directory 491." This paragraph further
states ( emphasis added) "Loads from CIU control logic
441 in the load path receive immediate access to
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Application 12/424,284
directory 491 without any intervening arbitrations, except
for the 3 way arbitration (ARB3) at 529" and that "A
load operation will win the 3 way (ARB3) arbitration at
529 and receive immediate access to the directory 429
ahead of the requests from competing requesters such
as RC state machines, cast out state machines, snoop
state machines and store queue 410." As shown in Figure
5A of the present specification, the other "competing
requesters" to arbitrator 529 are the store queue control
logic 410, the cache arbiter logic 420, and directory
arbiter logic 421.
Reply Br. 7.
Therefore, the "specification describe[ s] an invention
understandable to that skilled artisan and show[ s] that the inventor
actually invented the invention claimed" with respect to the claim
limitation "select a load request ... for immediate access to the
directory ahead of any requests selected by the store queue control
logic, the cache arbiter logic, or the directory arbiter logic." Ariad
Pharms., 598 F.3d at 1351; App. Br. 36.
Accordingly, we reverse the Examiner's rejection of claims 1,
6, 11, 16, and 21-36 under pre-AIA 35 U.S.C. § 112, first paragraph.
Pre-AJA 35 U.S.C. § 103
We have reviewed the Examiner's rejection in light of
Appellants' contentions and the evidence of record. We concur with
Appellants' contention that the Examiner erred in determining the
cited portions of Herbst and Guthrie collectively teach "core interface
unit control logic, coupled to the cache arbiter logic and directory
arbiter logic, that is configured to receive load requests from a core
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Application 12/424,284
load request bus associated with the processor element," as recited in
independent claim 1 ( emphasis added). See App. Br. 21-22; Reply
Br. 17-19.
The Examiner cites Herbst's interface 202 for teaching the
claimed "core interface unit control logic," and Herbst's decision
blocks 310 and 314 collectively for teaching the claimed "cache
arbiter logic." See Final Act. 6; Herbst Fig. 3, 5: 17-37, 6:56-8:6.
The Examiner finds "HERBST does not appear to explicitly disclose"
the claimed "directory arbiter logic," and cites Guthrie's directory 234
instead. See Final Act. 7; Guthrie ,r 39.
However, the Examiner does not show the cited Herbst and
Guthrie portions collectively teach "core interface unit control logic,
coupled to the cache arbiter logic and directory arbiter logic," as
required by clam 1 (emphasis added). See App. Br. 21-22; Reply Br.
17-19. Nor does the Examiner directly respond to Appellants'
argument about the above limitation.
Because the Examiner fails to provide sufficient evidence or
explanation to support the rejection, we are constrained by the record
to reverse the Examiner's rejection of claim 1.
Each of independent claims 6, 11, and 16 recites a claim
limitation that is substantively similar to the disputed limitation of
claim 1. See claims 6, 11, and 16. The Examiner applies the same
findings and conclusions to claims 1, 6, 11, and 16. See Final Act. 6-
17. Therefore, for similar reasons, we reverse the Examiner's
rejection of independent claims 6, 11, and 16.
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We also reverse the Examiner's rejection of corresponding
dependent claims 21-3 6.
DECISION
We reverse the Examiner's decision rejecting claims 1, 6, 11,
16, and 21-36 under (i) pre-AIA 35 U.S.C. § 112, first paragraph; and
(ii) pre-AIA 35 U.S.C. § 103.
REVERSED
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