Ex Parte Ghaghahi et al

Patent Trial and Appeal Board

Dec 12, 2013

11743162 (P.T.A.B. Dec. 12, 2013)

UNITED STATES PATENT AND TRADEMARKOFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
11/743,162 05/02/2007 Farshad Ghaghahi 06-0095 90006 6266
98440 7590 12/12/2013
Otterstedt, Ellenbogen & Kammer, LLP
P.O. Box 98
East Northport, NY 11731
EXAMINER
GORDON, MATTHEW E
ART UNIT PAPER NUMBER
2892
MAIL DATE DELIVERY MODE
12/12/2013 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE PATENT TRIAL
AND APPEAL BOARD
____________
Ex parte FARSHAD GHAGHAHI, SHAHRAM NIKOUKARY, and
HALFORD KOKICHI TOME
____________
Appeal 2011-004370
Application 11/743,162
Technology Center 2800
____________

Before BRADLEY R. GARRIS, KAREN M. HASTINGS, and
ROMULO H. DELMENDO, Administrative Patent Judges.

HASTINGS, Administrative Patent Judge.

DECISION ON APPEAL

Appellants appeal under 35 U.S.C. § 134 from the Examiner’s final
rejection of claims 1, 3, 4, 6-10, 12, 13, and 15-22. We have jurisdiction
over the appeal pursuant to 35 U.S.C. § 6(b).

Appeal 2011-004370
Application 11/743,162

2
Claims 1 and 22 are illustrative of the claimed subject matter:
1. An integrated circuit package comprising:
a top layer formed in a package substrate;
a first plurality of via groups formed in the top layer surrounding an
area on the top layer for an integrated circuit die;
at least one lower layer formed in the package substrate;
a lower via group formed in the lower layer below each of the first
plurality of via groups, respectively;
an electrical connection form in the lower layer between each lower
via group and the first plurality of via groups, respectively;
a ground connection formed in the integrated circuit package for each
lower via group to connect each lower via group to an electrical ground to
block electromagnetic interference;
an electrically conductive package cover having an area that encloses
the first plurality of via groups and is electrically connected to each of the
first plurality of via groups; and
a thermally and electrically conductive compound at least partially
filling a void between the integrated circuit die and the electrically
conductive package cover.

22. The integrated circuit package of claim 1, wherein a spacing
between adjacent via groups in the first plurality of via groups is made less
than one-tenth of a wavelength of a highest expected electromagnetic
interference (EMI) signal to thereby block EMI radiation.

The Examiner maintains, and the Appellants appeal, the following
rejections under 35 U.S.C. § 103(a):
1) claims 1, 3, 4, 6, 7, 10, 12, 13, 15, 16, and 19-22 as unpatentable
over Terui1 in view of Karnezos2;

1 U.S. Patent Application Publication No. 2001/0008301 A1, published July
19, 2001.
2 U.S. Patent Application Publication No. 2004/0119153 A1, published June
24, 2004.
Appeal 2011-004370
Application 11/743,162

3

2) claim 8, 9, 17, 18 as unpatentable over Terui in view of Karnezos,
and further in view of Canella.3

ANALYSIS
Upon consideration of the evidence on this record and each of
Appellants’ contentions, we find that the preponderance of evidence on this
record supports the Examiner’s conclusion that the subject matter of
Appellants’ claims is unpatentable over the applied prior art. We sustain the
above rejections based on the Examiner’s findings of fact, conclusions of
law, and rebuttals to Appellants’ arguments as expressed in the Answer.
We add the following for emphasis.
Appellants contend that Terui fails to teach the “via group” claim
language. The Examiner relied upon Terui’s “interconnections 7” to satisfy
this claim language (Ans. 4). Appellants however maintain the “patentee is
free to act as his own lexicographer . . . .” Thus, a via group “refers to a
conductive structure which at least partially passes through the package
substrate vertically (i.e., perpendicular to a plane of the substrate) for
electrically coupling two or more conductive layers residing in separate
planes” (Br. 8, 9). “Because item 7 (interconnects or wires) . . . do not pass
through the substrate but rather are formed on the back surface of the
substrate, they cannot be considered vias . . . .” Id.

3 U.S. Patent Application Publication No. 2004/0058470 A1, published
March 25, 2004.
Appeal 2011-004370
Application 11/743,162

4
We do not agree. Appellants have not established that the
Specification sets forth a special definition of “via group,” but even if it did,
this alleged special definition encompasses the structure of Terui. As the
Examiner aptly points out, “Fig. 5 of Terui clearly shows that
interconnection 7 includes a vertical portion that passes through the substrate
30” (Ans. 8).
Appellants counter the first plurality of via groups are not connected
to the lower via group and electrical ground because “through holes 5 are
electrically disconnected from intermediate layer 31, which is electrically
connected to ground . . . .” (Reply Br. 3) (original emphasis maintained).
The Examiner correctly explains the lower via group in Terui is connected to
an electrical ground. (Ans. 4) (See also Terui, ¶ [0019], [0026]). Because
the upper (first) and lower via groups are electrically also connected by item
7 (interconnect or wires), the first via group is connected both to the lower
via group and to electrical ground. This teaching applies to all of the Terui
embodiments (see, e.g., Fig. 5, where the item 7 interconnection grounds the
intermediate layer 31 to the grounded, electrode 18a).
Appellants also maintain that Terui teaches away from the addition of
an electrically conductive compound filling a void between the integrated
circuit die and the electrically conductive package cover, as taught by
Karnezos (Brief 9, 10). The Appellants argue Terui teaches an “insulating
adhesive 17,” thus teaching away from the addition of a thermally and
electrically conductive compound.
The “prior art’s mere disclosure of more than one alternative does not
constitute a teaching away from any of these alternatives because such
disclosure does not criticize, discredit, or otherwise discourage the solution
Appeal 2011-004370
Application 11/743,162

5
claimed . . . .” In re Fulton, 391 F.3d 1195, 1201 (Fed. Cir. 2004). Rather,
the Examiner established that one of ordinary skill in the art would have
been motivated to use an alternative compound that is both thermally and
electrically conductive because the compound would have provided the
same advantage of thermal dissipation (Ans. 5). Indeed, the Examiner cited
paragraph 143 of Karnezos, which explicitly states the thermally and
electrically conductive compound “improves[s] thermal dissipation” and
“establish[es] electrical connection of the heat spreader.” See, In re Harris,
409 F.3d 1339, 1341 (Fed. Cir. 2005) (whether a reference teaches away
from a claimed invention is a question of fact).
It is well established that ordinary creativity is presumed on the part of
one of ordinary skill in the art. See KSR Int’l Co. v. Teleflex Inc., 550 U.S.
398, 421 (2007) (“[a] person of ordinary skill is also a person of ordinary
creativity, not an automaton.”). A preponderance of the evidence supports
the Examiner’s determination that, one of ordinary skill in the art, using no
more than ordinary creativity, would have found it obvious to use a
thermally and electrically conductive compound to fill the void between the
circuit die and the electrically conductive package cover. See KSR, 550 U.S.
at 416 (“The combination of familiar elements according to known methods
is likely to be obvious when it does no more than yield predictable results.”).
Regarding claim 22, Appellants assert the “references cited by the
Examiner contain no teaching or suggestion that the spacing between
adjacent via groups in the first plurality of via groups was recognized as a
variable which achieves a recognized result with regard to the ability to
block EMI radiation” (Br. 11). Appellants did not, however, specifically
refute the Examiner’s reasonable determination that it would have been
Appeal 2011-004370
Application 11/743,162

6
well-known to one of ordinary skill in the art that the spacing of via
openings on a circuit board may be controlled to achieve shielding benefits
from EMI of certain wavelengths, nor have Appellants alleged or shown any
unexpected results to establish that the claimed spacing is critical (Ans. 9;
generally Br.). Cf. In re Peterson, 315 F.3d 1325, 1330 (Fed. Cir. 2003)
(“The normal desire of scientists or artisans to improve upon what is already
generally known provides the motivation to determine where in a disclosed
set of . . . ranges is the optimum combination . . . .”).
Accordingly, we affirm the Examiner’s rejections.
The Examiner’s decision is affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a).
AFFIRMED

cam