Ex Parte Gewirtzman et alDownload PDFPatent Trial and Appeal BoardOct 14, 201411600814 (P.T.A.B. Oct. 14, 2014) Copy Citation UNITED STATES PATENT AND TRADEMARK OFFICE UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 11/600,814 11/17/2006 Raanan Gewirtzman 3875.5100001 4488 26111 7590 10/15/2014 STERNE, KESSLER, GOLDSTEIN & FOX P.L.L.C. 1100 NEW YORK AVENUE, N.W. WASHINGTON, DC 20005 EXAMINER LI, SHI K ART UNIT PAPER NUMBER 2637 MAIL DATE DELIVERY MODE 10/15/2014 PAPER Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE ____________________ BEFORE THE PATENT TRIAL AND APPEAL BOARD ____________________ Ex parte RAANAN GEWIRTZMAN, DAVID IVANCOSKY, MOSHE LEVY, IGOR ELKANOVICH, OFFER SCHWARTSGLASS, and SIMON HOCHBAUM ____________________ Appeal 2012-0043581 Application 11/600,814 Technology Center 2600 ____________________ Before JEAN R. HOMERE, JOHNNY A. KUMAR, and CATHERINE SHIANG, Administrative Patent Judges. HOMERE, Administrative Patent Judge. DECISION ON APPEAL 1 Appellants identify the real party in interest as Broadlight, Ltd. App. Br. 3. Appeal 2012-004358 Application 11/600,814 2 STATEMENT OF THE CASE Appellants appeal under 35 U.S.C. § 134(a) from the Examiner’s Non-Final Rejection (mailed on March 28, 2011) of claims 1 and 3–32. Claim 2 has been canceled. App. Br. 3. We have jurisdiction under 35 U.S.C. § 6(b). We affirm. Appellants’ Invention Appellants invented an optical network unit (ONU) circuit (200) for transmitting upstream burst data at high rate and for receiving downstream continuous data at the high rate. In particular, the ONU circuit (200) has integrated therein a passive optical network (PON) processor (220) for controlling through a physical (PHY) layer adapter (210) an optical interface (250) that converts electrical signals into optical signals, and vice-versa. Fig. 2. The PHY layer adapter (210) includes a burst laser driver (310) for driving a laser diode and for handling the high rate upstream bust data. The PHY layer adapter also includes a limiting amplifier (320) for handling the high rate downstream data. Fig. 3. Further, the PON processor (220) is connected to the PHY layer adapter (250) via a first connection (230) for transferring high speed data, and via an internal bus (240) for transferring indication signals on the status of interface signals thereby allowing the PON processor (220) to process the upstream, and downstream high rate of data. Spec. 4, l. 7–27. Representative Claim Independent claim 1 is representative. It reads as follows: 1. An optical network unit (ONU) circuit fabricated on a single integrated circuit (IC), the ONU circuit comprising: Appeal 2012-004358 Application 11/600,814 3 a physical (PHY) layer adapter for interfacing with an optical interface for transmitting upstream burst data at a high rate and receiving downstream continuous data at a high rate, the optical interface converts optical signals to electrical signals and electrical signals to optical signals, wherein the PHY layer adapter includes: a burst laser driver for driving a laser diode and for handling the high rate upstream burst data; a continuous limiting amplifier for handling the high rate downstream continuous data; a passive optical network (PON) processor for controlling the optical interface through the PHY layer adapter and for processing upstream data and downstream data of the PON; a connection connected between the PON processor and the PHY layer adapter and for transferring high speed data; and an internal bus connected between the PON processor and the PHY layer adapter and for transferring indication signals on the status of the optical interface. Prior Art Relied Upon King US 5,812,572 Sept. 22, 1998 Chiang US 7,215,891 B1 May 8, 2007 Stiscia US 7,385,995 B2 June 10, 2008 Broadcom, BCM 8703 Product Brief (2003) (“Broadcom”). Rejections on Appeal The Examiner rejects the claims on appeal as follows: Claims 1, 4–7, and 14–18 stand rejected under 35 U.S.C. § 103(a) as being unpatentable over the combination of Chiang and Stiscia. Claim 3 stands rejected under 35 U.S.C. § 103(a) as being unpatentable over the combination of Chiang, Stiscia, and Broadcom. Appeal 2012-004358 Application 11/600,814 4 Claims 8–13 and 19–32 stand rejected under 35 U.S.C. § 103(a) as being unpatentable over the combination of Chiang, Stiscia, and King. ANALYSIS We consider Appellants’ arguments seriatim as they are presented in the Appeal Brief, pages 7–17, and the Reply Brief, pages 2–11.2 Dispositive Issue: Under 35 U.S.C. § 103, did the Examiner err in finding the proposed combination of Chiang and Stiscia teaches or suggests, a single integrated circuit (IC) containing, inter alia, a burst laser driver for handling a high rate upstream burst data, and a PON processor for processing upstream data and downstream data, as recited in claim 1? Appellants argue the proffered combination of references does not teach or suggest the disputed limitations emphasized above. App. Br. 9–13, Reply Br. 3–10. In particular, Appellants argue while Chiang discloses a single IC integrated in an optical transceiver, the IC is not enough to operate as a piece of network equipment, and the transceiver is not a single IC. App. Br. 8–9. Further Appellants argue although Chiang discloses a laser driver, it is not a burst laser driver capable of handling burst data. Id. at 8. Additionally, Appellants argue that because Chiang’s microcontroller is limited to processing a set of instructions for providing operational status of 2 Rather than reiterate the arguments of Appellants and the Examiner, we refer to the Appeal Brief (filed August 29, 2011), the Reply Brief (Filed December 30, 2011) and the Answer (mailed November 18, 2011) for the respective details. We have considered in this Decision only those arguments Appellants actually raised in the Briefs. Any other arguments Appellants could have made but chose not to make in the Briefs are deemed to be waived. See 37 C.F.R. § 41.37(c)(1)(vii) (2008). Appeal 2012-004358 Application 11/600,814 5 an operational transceiver, as opposed to a PON processor that can handle upstream and downstream traffic, the proposed combination of the microcontroller with Stiscia’s PON controller would change the principle of operation of the microcontroller. Id. at 12. In response, the Examiner finds Chiang’s disclosure of a single IC circuit containing a laser driver and a microprocessor for transmitting and receiving data, taken in combination with Stiscia’s PON processor, teaches the disputed limitations. Ans. 10–13. On the record before us, we do not find error in the Examiner’s obviousness rejection of claim 1. We note at the outset Appellants do not dispute the Examiner’s finding that Chiang discloses a single IC containing a laser driver circuit that interfaces with a controller having a microprocessor that processes data to be transmitted (Tx) as well as received data (Rx). However, Appellants contend that the laser driver is not a burst laser driver capable of handling high rate data burst, and the microprocessor does not handle high rate data. We do not agree with Appellants. First, as correctly noted by the Examiner, beside the indication that the burst laser driver is able to drive various types of lasers including Fabry-Perot (FP) laser, a distributed feedback (DFB) laser, and the like (Spec. 6, ll. 18–21), Appellants’ Specification does not provide any guidance as to what the high rate data burst entails. See Ans. 9–10. We thus find Chiang’s disclosure that the laser driver can be an FP laser or a DFB laser that operates over a wide range of data rates from 100 Mbps to 4.5 Gbps (Chiang, col. 3, ll. 33–39) teaches a laser driver for handling high rate data burst. Likewise, we find because the microcontroller interfaces with the laser driver handling high rate upstream burst data and the limiting amplifier handling high rate Appeal 2012-004358 Application 11/600,814 6 downstream data (Chiang, col. 3, ll. 33–45), the microprocessor processes high rate data burst as well. We therefore agree with the Examiner that the incorporation of Stiscia’s an integrated PON processor (240) in Chiang’s IC would have allowed Chiang’s system to be suitable for use in an optical network setting. Consequently, we find unpersuasive Appellants’ arguments that Stiscia’s teaching would change the manner of operation of Chiang’s microcontroller. Appellants are reminded that an argument that a system is rendered “unsuitable for its intended purpose” is a “teach away” argument. In re Gordon, 733 F.2d 900, 902 (Fed. Cir. 1984) (The court concluded that in effect, “French teaches away from the board’s proposed modification” because “if the French apparatus were turned upside down, it would be rendered inoperable for its intended purpose.”). The Federal Circuit has held “[a] reference may be said to teach away when a person of ordinary skill, upon reading the reference, would be discouraged from following the path set out in the reference, or would be led in a direction divergent from the path that was taken by the applicant.” In re Kahn, 441 F.3d 977, 990 (Fed. Cir. 2006) (quoting In re Gurley, 27 F.3d 551, 553 (Fed.Cir.1994)).3 In this 3 “If references taken in combination would produce a ‘seemingly inoperative device,’ . . . such references teach away from the combination and thus cannot serve as predicates for a prima facie case of obviousness.” McGinley v. Franklin Sports, Inc., 262 F.3d 1339, 1354 (Fed. Cir. 2001) (citation omitted); see also In re ICON Health & Fitness, Inc., 496 F.3d 1374, 1382 (Fed. Cir. 2007) (“a reference teaches away from a combination when using it in that combination would produce an inoperative result,” but the obviousness analysis must account for “modifications that one skilled in the art would make to a device borrowed from the prior art”) (citations omitted); In re Gordon, 733 F.2d 900, 902 (Fed. Cir. 1984) (finding no Appeal 2012-004358 Application 11/600,814 7 case, Appellants have presented no evidence that criticizes or even discourages from incorporating an integrated PON processor as disclosed Stiscia into Chiang’s IC. As discussed above, we find such combination would have instead enhanced the functionality of Chiang’s IC. We thus find the cumulative weight and the totality of the evidence on this record favor the Examiner’s position that the combined disclosures of Chiang and Stiscia would have taught or suggested the disputed limitations. For at least the aforementioned reasons, we find Appellants have not sustained the requisite burden on appeal of providing arguments or evidence persuasive of error in the Examiner’s rejection of representative claim 1. It therefore follows that Appellants have not shown that the Examiner erred in finding that the combination of Chiang and Stiscia renders claim 1 unpatentable. Because Appellants have not presented separate patentability arguments or have reiterated substantially the same arguments as those previously discussed for patentability of claim 1 above, claims 4–7 and 14– 18 fall therewith. See 37 C.F.R. § 41.37(c)(1)(vii)(2008). Regarding the rejection of claim 3, Appellants submit the combination of Chiang, Stiscia, and Broadcom does not teach or suggest a built-in self- test (BIST) for testing the PHY layer adapter. According to Appellants, while Broadcom discloses a BCM8703 containing built-in jitter for testing XAUI and PMD, these modules are independent of the PHY layer. App. Br. 14–15. This argument is unavailing. As noted by the Examiner, because the reason to modify a prior art device where the modification would render the device “inoperable for its intended purpose”). Appeal 2012-004358 Application 11/600,814 8 BCM8703 fully integrates a channel PHY, the self-test being performed therein teaches testing the physical layer. Ans. 14. Appellants have therefore failed to show error in the Examiner’s rejection of claim 3. Regarding the rejection of claims 19 and 26, Appellants argue the combination of Chiang, Stiscia, and King does not teach calibrating the ONU circuit. App. Br. 15. According to Appellants, while King discloses a calibration process, it would not be applicable to the Chiang-Stiscia system, which fails to teach a PON processor for handling high data rate. App. Br. 15–16. As discussed above, we find unpersuasive Appellants’ arguments as they pertain to the combination of Chiang, Stiscia. Further, because King’s calibration process would provide the Chiang-Stiscia system with a mechanism for calibrating modules in the IC system in an optical network setting, we agree with the Examiner that the proffered combination of references teaches or suggests the disputed limitations of claims 19 and 26. In light of the foregoing reasons, we sustain the Examiner’s rejections of claims 8–13 and 19–32. DECISION We affirm the Examiner’s rejections of claims 1 and 3–32 as set forth above. No time period for taking any subsequent action in connection with this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv). AFFIRMED llw Copy with citationCopy as parenthetical citation