Ex Parte Gerber

Patent Trial and Appeal Board

Nov 27, 2017

14087047 (P.T.A.B. Nov. 27, 2017)

United States Patent and Trademark Office
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O.Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
14/087,047 11/22/2013 Nir Gerber 133459/1173-118 3782
115309 7590 11/29/2017
W&T/Onalrnmm
EXAMINER
106 Pinedale Springs Way
Cary, NC27511
OBERLY, ERIC T
ART UNIT PAPER NUMBER
2184
NOTIFICATION DATE DELIVERY MODE
11/29/2017 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
patents @ wt-ip.com
us-docketing@qualcomm.com
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PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte NIR GERBER
Appeal 2017-005173
Application 14/087,047
Technology Center 2100
Before JOHN A. JEFFERY, DENISE M. POTHIER, and JASON J.
CHUNG, Administrative Patent Judges.
JEFFERY, Administrative Patent Judge.
DECISION ON APPEAL
Appellant appeals under 35 U.S.C. § 134(a) from the Examiner’s
decision to reject claims 1—23. We have jurisdiction under 35 U.S.C. § 6(b).
We reverse.
STATEMENT OF THE CASE
Appellant’s invention interconnects two secure digital (SD)-compliant
devices by passing signals between the devices with voltages lower than 1.8
volts mandated by the SD standard. This reduced voltage (1) increases
battery life, (2) reduces electromagnetic interference, and (3) reduces the
number of power rails and external level shifters that would otherwise be
needed. See generally Abstract; Spec. 15. Claim 1 is illustrative:
Appeal 2017-005173
Application 14/087,047
1. A method of interconnecting two secure digital
(SD) compliant devices, comprising:
coupling a transmitting output of a first SD
compliant device of two SD compliant devices to a
receiving input of a second SD compliant device; and
operating according to an SD standard except that
voltage levels at the transmitting output are less than 1.8
volts to achieve a logical high for signals.
THE REJECTIONS
The Examiner rejected claims 1, 2, 5, and 17—19 under 35 U.S.C.
§ 102(a)(1) as anticipated by SD Group, SD Specifications Pt. 1, Physical
Layer Simplified Specification, Ver. 4.10 (Jan. 22, 2013) (“SD Spec.”).
Final Act. 2-4.1
The Examiner rejected claims 6—8, 13, 14, and 16 under 35 U.S.C.
§ 103(a) as unpatentable over SD Specification and Asfur (US
2010/0138580 Al; June 3, 2010). Final Act. U-6.
The Examiner rejected claims 3, 4, and 20 under 35 U.S.C. § 103(a)
as unpatentable over SD Specification and Luo (US 2007/0147157 Al; June
28, 2007). Final Act. 6-9.
The Examiner rejected claims 9 and 10 under 35 U.S.C. § 103(a) as
unpatentable over SD Specification, Asfur, and Luo. Final Act. 9—11.
The Examiner rejected claims 11 and 12 under 35 U.S.C. § 103(a) as
unpatentable over SD Specification, Asfur, Jeon (US 2010/0322007 Al; Dec.
23, 2010), and Luo. Final Act. 12—13.
1 Throughout this opinion, we refer to (1) the Final Rejection mailed April
26, 2016 (“Final Act.”); (2) the Appeal Brief filed July 20, 2016 (“App.
Br.”); (3) the Examiner’s Answer mailed December 15, 2016 (“Ans.”); and
(4) the Reply Brief filed February 8, 2017 (“Reply Br.”).
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Application 14/087,047
The Examiner rejected claim 15 under 35 U.S.C. § 103(a) as
unpatentable over SD Specification, Asfur, and Ghaly (US 2014/0258796
Al; Sept. 11,2014). Final Act. 13-14.
The Examiner rejected claims 21—23 under 35 U.S.C. § 103(a) as
unpatentable2 over Asfur and SD Specification. Final Act. 14—18.
THE ANTICIPATION REJECTION
Regarding independent claim 1, the Examiner finds that SD
Specification discloses coupling a transmitting output of a first SD-
compliant device, namely the SD port of a host in which a card is inserted, to
a receiving input of a second SD-compliant device. Final Act. 2; Ans. 5—6.
According to the Examiner, SD Specification indicates that Supply Voltage
2 (VDD2) is from 1.70 V to 1.95 V on Pin #14 in Table 3-3, and (2) it is
well known that binary logic levels “correspond to” the supply voltage.
Final Act. 2. To evidence this correspondence, the Examiner cites a
Wikipedia entry on logic levels3 and an excerpt from a book on electric
circuits.4 Ans. 7—8. In light of these findings, SD Specification is said to
operate according to an SD standard except that voltage levels at the
transmitting output are less than 1.8 volts to achieve a logical high for
signals. Id.
2 Although the Examiner indicates that claims 21—23 are anticipated despite
their rejection under § 103 (Final Act. 14), we nonetheless presume that
these claims were rejected as obvious over the cited references. Accord
App. Br. 13 (assuming an obviousness rejection despite the Examiner’s
anticipation language).
3 “Logic Level,” Wikipedia (last modified Apr. 20, 2016).
4 Tony R. Kuphaldt, Lessons in Electric Circuits, Vol. IV-Digital 90-
99 (4th ed. 2007) (“Kuphaldt”).
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Application 14/087,047
Appellant argues, among other things, that although there is an
overlap in the range of VDD2 in the SD Specification, the signaling voltage
is not equal to, nor does it specifically correspond to, the supply voltage,
particularly in view of the reference explicitly distinguishing these voltages.
App. Br. 8—9. Appellant adds that the Examiner’s purported “connection”
between logical signaling and supply voltages is not only not necessarily
present in SD Specification, the reference’s disclosure of using line drivers
and pullup resistors to convert internal voltages further indicates that the
signalling voltage is not necessarily the supply voltage. Reply Br. 4.
ISSUE
Under § 102, has the Examiner erred in rejecting claim 1 by finding
that SD Specification discloses interconnecting two SD compliant devices
by operating according to an SD standard except that voltage levels at the
transmitting output are less than 1.8 volts to achieve a logical high for
signals?
ANALYSIS
As noted above, the Examiner relies principally on SD Specification’s
Table 3-3 on page 13 that is a pin assignment for Ultra High Speed Phase II
(UHS-II) cards. See Final Act. 2; see also SD Specification 13 (“3.7.2 UHS-
II Pin Assignment”). We emphasize that the Examiner’s rejection is based
on the UHS-II card—not the UHS-I card that is described in SD
Specification’s Section 3.9 on page 15 and cited on pages 9 and 10 of the
Appeal Brief. We, therefore, confine our discussion to the UHS-II card
relied upon in the rejection.
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Application 14/087,047
As shown in Table 3-3, Pins 4 and 14 are assigned to “Supply
Voltage” (VDD1) and “Supply Voltage 2” (VDD2), respectively. SD
Specification 13. It is the latter supply voltage, namely VDD2, that is said to
anticipate the recited voltage level of less than 1.8 volts to achieve a logical
high for signals. Final Act. 2.
This finding is problematic on this record. To be sure, VDD2 ranges
from 1.7 to 1.95 volts and, therefore, is at least partially within the recited
voltage range, namely voltages from 1.7 volts to some voltage less than 1.8
volts. But to say that VDD2 necessarily achieves a logical high for signals
as required for anticipation5 strains reasonable limits on this record. That
SD Specification distinguishes signaling voltages and supply voltages only
further undercuts the notion that these voltages are necessarily the same.
See SD Specification 20 § 3.10.1 (listing signaling voltages in connection
with UHS-II card operation modes). Notably, the lowest signaling voltage
listed for the UHS-II card is 1.8 volts, which is not less than 1.8 volts as
claimed. See id. So even if this signaling voltage matched the supply
voltage (a finding that has not been substantiated on this record), it still
would not satisfy the recited signal voltage.
The Examiner’s reliance on the two additional documents to show the
known “correspondence” between binary logic levels and the supply voltage
(Ans. 7—8) is unavailing, at least with respect to anticipation. Although
Kuphaldt notes on page 90 that “high” and “low” logic states are ideally full
5 “Inherency . . . may not be established by probabilities or possibilities. The
mere fact that a certain thing may result from a given set of circumstances is
not sufficient.” In re Robertson, 169 F.3d 743, 745 (Fed. Cir. 1999)
(citations omitted).
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Application 14/087,047
power supply voltage and zero, respectively, that does not mean that VDD2
is necessarily a signaling voltage for UHS-II cards. Not only is there
another supply voltage for these cards in Table 3-3, namely VDD1, the fact
that SD Specification explicitly states that UHS-II card signaling voltages
are 3.3 volts and 1.8 volts on page 20 only further undercuts the Examiner’s
finding that VDD2 necessarily matches the logical high for signals, let alone
voltages lower than 1.8 volts.
The Wikipedia document fares no better in this regard. Notably, this
document was published after Appellant’s filing date and, as a non-peer-
reviewed document, has low probative value. See Bing Shun Li v. Holder,
400 F. App’x 854, 857 (5th Cir. 2010) (unpublished) (noting Wikipedia’s
unreliability and citing Badasa v. Mukasey, 540 F.3d 909, 910-11 (8th Cir.
2008)); see also Ex parte Three-Dimensional Media Group, Ltd., No. 2009-
004087, 2010 WF 3017280 (BPAI 2010) (non-precedential), at *17
(“Wikipedia is generally not considered to be as trustworthy as traditional
sources for several reasons, for example, because (1) it is not peer reviewed;
(2) the authors are unknown; and (3) apparently anyone can contribute to the
source definition”).
But leaving aside the Wikipedia document’s low probative value, the
fact that page 2 of this document notes that high voltage levels for CMOS
and TTF technologies can match the supply voltage does not mean that is
necessarily the case in SD Specification. That Wikipedia also notes that
internal voltages can be converted to standard line levels as Appellant
indicates (Reply Br. 4) only further undercuts the Examiner’s position in this
regard.
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Application 14/087,047
In short, although the devices in SD Specification operate according
to an SD standard, the Examiner has not shown that the voltage level at a
device’s transmitting output in SD Specification is necessarily less than 1.8
volts to achieve a logical high for signals as claimed.
Therefore, we are persuaded that the Examiner erred in rejecting (1)
independent claim 1; (2) independent claim 17 that recites commensurate
limitations; and (3) dependent claims 2, 5, 18, and 19 for similar reasons.
THE OBVIOUSNESS REJECTIONS
Because the Examiner has not shown that the additional cited prior art
cures the foregoing deficiencies of SD Specification noted in connection
with claim 1, we will not sustain the obviousness rejections of claims 3, 4,
6—16, and 20—23 (Final Act. 4—18) for similar reasons.
CONCLUSION
The Examiner erred in rejecting (1) claims 1, 2, 5, and 17—19 under
§ 102, and (2) claims 3, 4, 6—16, and 20-23 under § 103.
DECISION
We reverse the Examiner’s decision to reject claims 1—23.
REVERSED
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