Ex Parte Gautam et al

Patent Trial and Appeal Board

Feb 4, 2016

12648731 (P.T.A.B. Feb. 4, 2016)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE
12/648,731 12/29/2009
30424 7590 02/08/2016
ADDMG - ST (first filed US/ Asia)
255 S. Orange A venue, Suite 1401
Orlando, FL 32801
FIRST NAMED INVENTOR
Akhilesh GAUTAM
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
08-IND-186 (52698) 4346
EXAMINER
NORMAN, JAMES G
ART UNIT PAPER NUMBER
2827
NOTIFICATION DATE DELIVERY MODE
02/08/2016 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address( es):
creganoa@addmg.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Exparte AKHILESH GAUTAM and CHIRAG GULATI 1
Appeal2014-001334
Application 12/648,731
Technology Center 2800
Before PETER F. KRATZ, GRACE KARAFFA OBERMANN, and
CHRISTOPHER C. KENNEDY, Administrative Patent Judges.
KENNEDY, Administrative Patent Judge.
DECISION ON APPEAL
STATEMENT OF THE CASE
This is an appeal under 35 U.S.C. § 134(a) from a final rejection of
claims 18, 20, 22, 24, 30, 31, 33, 35, and 37. We have jurisdiction under
35 U.S.C. § 6(b).
We AFFIRM.
1 According to the Appellants, the real party in interest is
STMicroelectronics Pvt. Ltd. App. Br. 1.
Appeal2014-001334
Application 12/648,731
The subject matter on appeal relates to data storage systems (such as
SRAM) and, more specifically, to the sensing device used for sensing the
stored data. Spec. i-f 1; Claim 18. Claim 18 is reproduced below from page
15 (Appendix A) of the Appeal Brief:
18. A system comprising:
a dual bit line data storage sub-system; and
a device configured to sense data in said dual bit line data storage
sub-system, said device comprising
a pull-down circuit configured to discharge both bit lines of a
selected data storage cell, and comprising
a first controlled switch coupled between a first bit line of
the bit lines and a common node and having a control
terminal coupled to a second bit line of the bit lines and a
conduction terminal coupled to a common terminal, and
a second controlled switch coupled between the second bit
line and the common node and having a control terminal
coupled to the first bit line and a conduction terminal
coupled to the common terminal,
a pull-up circuit coupled to both bit lines and configured to
compensate for the discharge of one of the bit lines that is at
a voltage threshold corresponding to a first logic state, and
a sensing circuit coupled to both the bit lines and configured
to sense the dual bit lines in the selected data storage cell and
compnsmg
a sixth controlled switch coupled between the common
terminal and an output node and having a control terminal
coupled to a first bit line of the bit lines, and
a seventh controlled switch coupled between a supply
voltage and the output node and having a control terminal
coupled to a second bit line of the bit lines.
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Appeal2014-001334
Application 12/648,731
ANALYSIS
All claims on appeal are rejected under 35 U.S.C. § 103(a) as being
unpatentable over Iyengar (US 5,748,556, issued May 5, 1998) in view of
Haraszti (US 4,169,233, issued Sept. 25, 1979). The Appellants do not
argue the claims separately, so the claims stand or fall together. 37 C.F.R.
§ 41.37(c)(l)(iv). We select claim 18, reproduced above, as representative
of the rejected claims.
After review of the evidence in the appeal record and the opposing
positions of the Appellants and the Examiner, we determine that the
Appellants have not identified reversible error in the Examiner's rejection.
Accordingly, we affirm the rejection for reasons set forth by the Examiner in
the Final Action dated November 5, 2012, the Advisory Action dated
January 23, 2013, and the Answer. See generally Final Act. 2-14; Advisory
Act. 2; Ans. 3-8. We add the following for emphasis and completeness.
The Appellants first argue that I yen gar does not disclose "a sixth
controlled switch coupled between the common terminal and an output
node." App. Br. 10-12; Claim 18 (emphasis added). The Appellants
concede that transistor 58T, see Iyengar Fig. 3, "may be coupled to!!.
common terminal," but they assert that it "is not coupled to the common
terminal as defined in the claims," i.e., "the same common terminal to which
a conduction terminal of the first controlled switch is coupled, and to which
a conduction terminal of the second controlled switch is coupled." App. Br.
11-12 (emphases in original). In the Reply Brief, the Appellants concede
that Iyengar and Haraszti "may disclose a respective ground reference," but
argue that "both Iyengar et al. and Haraszti leave open the possibility of
different ground references." Reply Br. 2.
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Appeal2014-001334
Application 12/648,731
We are not persuaded by the Appellants' argument. The "possibility
of different ground references" in the diagrams does not support a
conclusion of nonobviousness if a person of ordinary skill in the art would
have interpreted the diagrams as having a single ground reference. As the
Examiner explains in the Answer, a person of ordinary skill in the art would
have understood that the relied-upon diagrams have only a single ground,
despite the fact that the diagrams do not literally show a single ground. Ans.
3. As the Examiner points out, id. at 4---6, both Iyengar and Haraszti-like
the instant Specification-use the international symbol for ground, which is
commonly understood to imply a single ground. Compare Iyengar Figs. 2 &
3 and Haraszti Fig. 9 with Spec. Fig. 4. The Appellants have not
persuasively rebutted the Examiner's finding that a person of ordinary skill
would have understood the figures of Iyengar and Haraszti to imply a single
ground ("common terminal"). Nor have the Appellants provided a
persuasive reason that a person of ordinary skill would have understood the
figures of Iyengar and Haraszti to have different meanings than Figure 4 of
the instant Specification, notwithstanding the fact that all of the figures use
the same international symbol for ground. Thus, we are not persuaded that
the prior art does not teach or otherwise render obvious the use of a common
terminal as recited by claim 18.
In the Reply Brief, the Appellants argue that "the Examiner
mischaracterized Haraszti," and that "Vss is a negative supply voltage,"
rather than a ground. Reply Br. 2. We do not find that argument persuasive
because Haraszti expressly teaches that ground is an example of Vss·
Haraszti at 3:62---64.
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Appeal2014-001334
Application 12/648,731
The Appellants also argue that ( 1) "a person having ordinary skill in
the art would not tum to a sense amplifier to compensate for the effects of
electrical parameter non-uniformities, as in Haraszti to combine with a tri-
state driver for isolating sense amplifiers from an internal data bus, as in
Iyengar," and (2) combining Iyengar and Haraszti "would change the
operability of Iyengar." App. Br. 12-13. We are not persuaded by those
arguments because the Appellants provide no evidence or persuasive
technical reasoning to support them. Cf In re Pearson, 494 F.2d 1399, 1405
( CCP A 197 4) ("Attorney's arguments in a brief cannot take the place of
evidence."). In any event, the Examiner finds that Iyengar teaches a sense
amplifier and that Haraszti teaches an improved sense amplifier, and that
"[a Jn improvement or benefit of a combination is the best motivation to
combine." Ans. 7. The Examiner further finds that the combination would
improve the operability of Iyengar rather than change the operability in a
way that supports nonobviousness. Id. at 7-8. The Appellants' arguments
provide no basis to reject those findings.
Finally, the Appellants argue that the Examiner fails to support the
contention that Iyengar modified by Haraszti would create a sense amplifier
with soft error protection. App. Br. 13. The Examiner, however, relies on
Haraszti's teaching that "[t]he sense amplifier of the present invention ...
provid[ es] self-compensation for non-uniformities of electrical parameters,"
i.e., error protection. Ans. 8 (citing Haraszti at Abstract). The Appellants do
not provide any evidence or persuasive technical reasoning to show that
I yen gar as modified by Haraszti would not possess the properties identified
by the Examiner. In any event, the Examiner also finds that Haraszti's sense
amplifier is improved in various other ways that would have likewise
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Appeal2014-001334
Application 12/648,731
motivated a person of ordinary skill in the art to combine the teachings of
Haraszti with Iyengar. E.g., Ans. 7-8. Accordingly, the Appellants'
arguments do not persuade us that a person of ordinary skill in the art would
not have been motivated to combine the prior art references.
Based on the arguments presented, we discern no reversible error in
the Examiner's rejection. We therefore affirm the rejection of claims 18, 20,
22, 24, 30, 31, 33, 35, and 37.
CONCLUSION
We AFFIRM the Examiner's rejection of claims 18, 20, 22, 24, 30,
31, 33, 35, and 37.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a).
AFFIRMED
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