Ex Parte Garney et alDownload PDFBoard of Patent Appeals and InterferencesJun 20, 200810888665 (B.P.A.I. Jun. 20, 2008) Copy Citation UNITED STATES PATENT AND TRADEMARK OFFICE ____________ BEFORE THE BOARD OF PATENT APPEALS AND INTERFERENCES ____________ Ex parte JOHN GARNEY and JOHN S. HOWARD ____________ Appeal 2008-0279 Application 10/888,665 Technology Center 2100 ____________ Decided: June 20, 2008 ____________ Before JAMES D. THOMAS, LANCE LEONARD BARRY, and ALLEN R. MACDONALD, Administrative Patent Judges. THOMAS, J., Administrative Patent Judge. DECISION ON APPEAL This is an appeal under 35 U.S.C. § 134(a) from the Examiner's final rejection of claims 1 through 24. We have jurisdiction under 35 U.S.C. § 6(b). The record in this application reflects that a terminal disclaimer was filed on September 15, 2005. Appeal 2008-0279 Application 10/888,665 2 As best representative of the disclosed and claimed invention, independent claim 13 is produced below: 13. An input/output device for communicating data, comprising: a memory adapted to buffer a single transfer request received during a transaction between a host controller and the device; a hub controller that performs the single transfer request between the device and an agent to generate a result; wherein the device receives a transfer inquiry from the host controller; and a control unit that determines whether the transfer inquiry corresponds to the result. The following references are relied on by the Examiner: Tipley 5,533,204 Jul. 2, 1996 James 6,108,739 Aug. 22, 2000 (filed Aug. 29, 1996) Claims 1 through 5 and 13 through 17 stand rejected under 35 U.S.C. § 102(b) as being anticipated by Tipley. In a second stated rejection, Tipley is utilized with James in a rejection under 35 U.S.C. § 103 to reject claims 6 through 12 and 18 through 24. Rather than repeat the positions of the Appellants and the Examiner, reference is made to the Brief and Reply Brief for the Appellants’ positions and to the Answer and Supplemental Answer for the positions of the Examiner. OPINION For the reasons set forth by the Examiner in the Answer and Supplemental Answer, we sustain the first and second stated rejections that Appeal 2008-0279 Application 10/888,665 3 encompass claims 1 through 24 on appeal. We add the following for emphasis and embellishment. We agree with the Examiner’s correlations of Tipley’s CPU subsystem 20 to the claimed host controller as well as the claimed hub comprising the PCI bridge 22 and/or alternatively the expansion bus chip set 48 which also acts as a bridge in the reference. Likewise, we also agree that the plurality of input/output devices in Tipley’s Figure 1 correspond to the claimed agents. Furthermore, the PCI bridge 22 according to Tipley’s teachings may be considered as a posting master within the context of PCI bus terminology and the expansion bus chip set 48 as the corresponding hub of the claims on appeal as well as the respective input/output devices 52 in Figure 1 as the respective agents. To the extent broadly recited in the claims on appeal, the terms “host controller” and “hub” and “agent” may be broadly interpreted in the manner such as we just did as well as the manner in which the Examiner did in a more straightforward approach. There are no structural distinctions recited in the claims as to these terms to distinguish them over the functionalities of the correlated elements in Tipley. The significant factor as well regarding Tipley’s teachings is that the correspondence of his split transaction protocol is consistent with the disclosed invention which is very abstractly recited in terms of the dialogue between the recited devices in the claims on appeal. As best set forth in the Supplemental Answer, the Examiner has correlated the claimed transfer request, transaction, and transfer inquiries of the respective devices in the manner recited in the claims to those teachings that are in Tipley. Appeal 2008-0279 Application 10/888,665 4 As to the features of dependent claim 4, the Examiner has correctly correlated the latch 45 and the buffers 41 in Figure 2B of Tipley to achieve the claimed buffering functions. Conventionally, PCI architectural considerations for the bus protocol require bridges that have buffers in them anyway. Because Tipley requires a split transaction protocol as a unique modification to traditional PCI protocols, intermediate, short latency dialogues must be stored in an intermediate manner between the split transaction requirements of longer latency device dialogues. Because the middle of page 5 of the Reply Brief indicates that the Appellants have discussed the features of claims 4, 5, 16, and 17 together in the principal Brief, they are considered to fall together for appeal purposes and not to have been argued separately as urged. Likewise, because no other arguments are presented in any manner as to any other claim within claims 1 through 5 and 13 through 17 in the first stated rejection, they are considered to fall with our consideration of the corresponding teachings of independent claims 1 and 13 on appeal. We turn now to the second stated rejection of various dependent claims as being obvious over Tipley and James. The arguments presented in the Brief and Reply Brief do not argue that these references are not properly combinable within 35 U.S.C. § 103. In comparison to the Examiner’s detailed correlation of the respective features of representative argued dependent claims 6, 9, 10, 12, 18, and 19, the nature of the positions in the Brief and Reply Brief appears to critique the Examiner’s analysis and correlations rather than convince us of any error in the Examiner’s approach to proving the unpatentability of the respective claims. Appellants do not Appeal 2008-0279 Application 10/888,665 5 appear to directly address the merits of the Examiner’s correlations from the references to the claimed features. Moreover, even the Examiner’s initial statement of the rejection on pages 7 and 8 of the Answer explains in a brief manner the improvements that James provides for PCI bus protocols over even those improvements disclosed in Tipley. James, like Tipley, improves upon the split transaction capabilities such as to avoid starvation and deadlock issues. Because PCI bus protocols are improved upon in both references, the artisan is well apprised that conventional data structures associated with the standard PCI protocol would be built upon as well. These include device IDs or addresses, status codes, primary and secondary latency timers, and implied comparisons to go with them, for example. From a system’s perspective, the system of Figure 1, for example, of James corresponds to the system environment in Figure 1 of Tipley to include the use of bridges as well as computer/host adaptors. Prior art Figure 2 shows a time stamp as a data structure of the first and second transmitted transactions in a split-response bus architecture of James. Figure 10 also illustrates the modification of the data structure to include a time of birth of the transaction. At column 7 the discussion of Figure 2 in James relates directly to the claimed status fields, the time stamp, the time stamp field, and the like. Thus, the Examiner’s reliance upon the discussion at the bottom of column 12 and the bulk of the discussion at column 13 as related to Figures 10 and 11 of James correspond to the argued features disputed among the many dependent claims before us that are argued by Appellants. An artisan’s reading of these discussions would clearly indicate at least impliedly the need for comparing times. Certain packets of information, Appeal 2008-0279 Application 10/888,665 6 such as the oldest ones, are processed first, thus indicating a comparison of given times with respect to a time stamp or time set. The Examiner’s reliance upon the timeout protocol in the paragraph bridging columns 13 and 14 indicates an implied comparison of the data structures in the dialogue sent and received. The predicate of the artisan’s understanding of Tipley and of the combination of Tipley with James is bottomed upon an artisan’s basic understanding of standard PCI bus protocols which both references build upon. The Tipley and James combination compels the artisan’s conclusion of obviousness of the argued claims within 35 U.S.C. § 103 once the split transaction protocol features of both references are considered together. In view of the foregoing, the decision of the Examiner rejecting various claims on appeal under 35 U.S.C. § 102 and 35 U.S.C. § 103 is affirmed. No time period for taking any subsequent action in connection with this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv). AFFIRMED tdl INTEL CORPORATION c/o INTELLEVATE, LLC P.O. BOX 52050 MINNEAPOLIS MN 55402 Copy with citationCopy as parenthetical citation