Ex Parte Gardner

Board of Patent Appeals and Interferences

Sep 23, 2009

10903613 (B.P.A.I. Sep. 23, 2009)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________
BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________
Ex parte ROBERT G. GARDNER
____________
Appeal 2008-005204
Application 10/903,6131
Technology Center 2100
____________
Decided: September 23, 2009
____________
Before LEE E. BARRETT, JEAN R. HOMERE, and JOHN A. JEFFERY,
Administrative Patent Judges.

BARRETT, Administrative Patent Judge.

DECISION ON APPEAL
This is a decision on appeal under 35 U.S.C. § 134(a) from the final
rejection of claims 1-16. We have jurisdiction pursuant to 35 U.S.C. § 6(b).

1 Filed July 31, 2004, titled "Virtualization Of A Non-Privileged
Instruction That Behaves Differently When Executed By Privileged Code
Than By Non-Privileged Code," now published application
US 2006/0095904 A1, published May 4, 2006. The real party in interest is
Hewlett-Packard Development Company, LP. Br. 1.
Appeal 2008-005204
Application 10/903,613

2
We affirm-in-part.
STATEMENT OF THE CASE
The invention
The invention relates to a virtual monitor and method for virtualizing
a "non-privileged" computer instruction having at least two types of
execution behavior, depending on prior events and on a current privilege
level. The invention is described in more detail in the Findings of Fact.

The claims
Claims 1, 9, and 10 are reproduced below:
1. A method for virtualizing a non-privileged computer instruction
with at least two types of execution behavior, depending on prior
events and on a current privilege level, the method comprising:
detecting a first event that causes a first type of execution
behavior upon subsequent execution of the non-privileged instruction;
configuring a detection mechanism that detects subsequent
execution of the non- privileged instruction;
when a second event is detected, determining whether or not, by
accessing the detection mechanism, the non-privileged instruction was
executed following occurrence of the first event; and
when the non-privileged instruction is determined to have
executed following occurrence of the first event, emulating the first
type of execution behavior.

9. A virtual monitor that includes one or more routines that carry
out the method of claim 1.

10. A virtual monitor that virtualizes a non-privileged computer
instruction with at least two types of execution behavior, depending
on prior events and on a current privilege level, by:
Appeal 2008-005204
Application 10/903,613

3
detecting a first event that causes a first type of execution
behavior upon subsequent execution of the non-privileged instruction;
configuring a detection mechanism that detects subsequent
execution of the non- privileged instruction;
when a second event is detected, determining whether or not, by
accessing the detection mechanism, the non-privileged instruction was
executed following occurrence of the first event; and
when the non-privileged instruction is determined to have
executed following occurrence of the first event, emulating the first
type of execution behavior.

The references

Hideki Eiraku and Yasuhi Shinjo, Running BSD Kernels as User
Processes by Partial Emulation and Rewriting of Machine
Instructions, Proceedings of BSDCon '03 (Sept. 8-12, 2003)
("Eiraku").

Admitted prior art in Appellant's published application
US 2006/0095904 A1, published May 4, 2006 ("APA").

The rejections
Claims 9-16 stand rejected under 35 U.S.C. § 101 as being directed to
nonstatutory subject matter.
Claims 1 and 10 stand rejected under 35 U.S.C. § 102(b) as being
anticipated by Eiraku.
Claims 2-9 and 11-16 stand rejected under 35 U.S.C. § 103(a) as
unpatentable over Eiraku and the APA.
PATENT ELIGIBLE SUBJECT MATTER -- 35 U.S.C. § 101
It is now clear that the four categories of "process, machine,
manufacture, or composition of matter" define the explicit scope and reach
of patent eligible subject matter under 35 U.S.C. § 101. See In re Nuijten,
Appeal 2008-005204
Application 10/903,613

4
500 F.3d 1346, 1354 (Fed. Cir. 2007), reh’g denied en banc, 515 F.3d 1361
(Fed. Cir. 2008), cert. denied, 129 S. Ct. 70 (2008) ("If a claim covers
material not found in any of the four statutory categories, that claim falls
outside the plainly expressed scope of § 101 even if the subject matter is
otherwise new and useful."). Thus, a "signal" cannot be patentable subject
matter because it is not within any of the four categories. Id. at 1357.
Similarly, a "paradigm" does not fit within any of the four categories.
In re Ferguson, 558 F.3d 1359, 1366 (Fed. Cir. 2009).
"Software" per se is similarly not within any of the four statutory
categories and is not patent eligible subject matter. See In re Chatfield,
545 F.2d 152, 159 (CCPA 1976) (Rich, J., dissenting) ("It has never been
otherwise than perfectly clear to those desiring patent protection on
inventions which are new and useful programs for general purpose
computers (software) that the only way it could be obtained would be to
describe and claim (35 U.S.C. § 112) the invention as a 'process' or a
'machine.'"). It is now also common to claim software as a "manufacture"
by reciting storing program code stored on a tangible medium that, when
executed, will perform a method. But, executable code per se is not a
"manufacture" under § 101.
Claim 9 is directed to a "virtual monitor that includes one or more
routines that carry out the method of claim 1." Despite the reference to
another claim and Appellant’s characterization of claim 9 as dependent
(Br. 3-4), claim 9 is considered to be an independent claim because it not in
the statutory class of a method as is claim 1. There is no question of
definiteness, but only how the claims should be treated for fee collection
purposes, which is not a matter within the Board's jurisdiction. See Ex parte
Appeal 2008-005204
Application 10/903,613

5
Moelands, 3 USPQ2d 1474, 1477 (BPAI 1987) (Examiner-in-Chief Lovell,
dissenting in part); Ex parte Porter, 25 USPQ2d 1144, 1147 (BPAI 1992).
See Claim 5 in In re Warmerdam, 33 F.3d 1354, 1358 (Fed. Cir. 1994).
Independent claims 9 and 10 are directed to a "virtual monitor" for
performing certain method steps. The virtual monitor is not a "process"
under § 101 because it is not a series of steps. The virtual monitor is not
hardware and is not a "machine" under § 101 because no structure is
claimed. The virtual monitor is not a "manufacture" or a "composition of
matter" under § 101 because it does not comprise tangible physical matter.
Accordingly, the "virtual monitor" is just a description of something that
does not fit within any statutory category and is not patent eligible subject
matter. It appears that the "virtual monitor" refers to software and, as noted,
software per se is not patent eligible subject matter. The present state of the
law supports the rejection. The Board follows the law, even if it is
inconsistent with the Guidelines.
Appellant argues that it is absurd that the result would be different if
the claims recited "stored in a computer-readable medium." Reply Br. 9.
A "computer-readable medium," however, is clearly classifiable as a
manufacture or machine and under the present state of the case, this makes a
difference.
Appellant has not shown error in the Examiner's rejection of
claims 9-16 as being directed to unpatentable subject matter. The rejection
of claims 9-16 is affirmed.

FINDINGS OF FACT
Disclosed invention
Appeal 2008-005204
Application 10/903,613

6
The Specification describes that the Intel IA-64 architecture provides
a cover instruction to facilitate register stack management and stack frame
allocation by interrupt handling routines. Spec. ¶ [0003].2
"Virtual monitors are low-level software systems that run directly
above the hardware level of a computer system. A virtual monitor is
intended to provide a virtual hardware interface to one or more operating
systems." Spec. ¶ [0004].
The Specification describes the problem of handling the cover
instruction with virtual monitors:
[0005] Virtual monitors designed for the IA-64 architecture normally
run at privilege level 0, the highest privilege level provided by an
IA-64 processor. In general, operating systems are also designed to
execute at privilege level 0. However, a virtual monitor is designed to
provide an interface that virtualizes privilege level, so that an
operating system can be run at a lower privilege level, for example,
privilege level 1, so that the virtual monitor can trap attempts by the
operating system to execute privileged instructions and access
privileged memory. By trapping privileged-instruction execution and
privileged-memory access, the virtual monitor can emulate privileged
instructions provided by the virtual-monitor interface, but not
supported by the hardware, and can juggle system resources between
concurrently running operating systems that are developed to have full
and complete control of machine hardware.

[0006] The cover instruction is a special problem for virtual monitors
because it is not privileged, and can be executed both by privilege-
level-0 virtual-monitor routines as well as by lower-privilege-level
operating system routines. Therefore, a virtual monitor cannot easily
trap attempts by an operating system to execute the cover instruction.
However, in general, the operating system assumes that it can raise
the privilege level to machine privilege level 0, while, in a virtualized
environment controlled by a virtual monitor, the operating system is,

2 We refer to paragraphs of published application US 2006/0095904.
Appeal 2008-005204
Application 10/903,613

7
in fact, running at virtual privilege level 0 and machine privilege level
1 or an even lower privilege level. Therefore, when the operating
system executes a cover instruction, it expects that the contents of a
current-frame-marker register are copied to a special, privileged
control register when a field within another, privileged register is set
to a particular value. But, because the operating system is actually
executing at privilege level 1 or lower, the cover instruction does not
copy the contents of the current-frame-marker register to the
privileged control register. Thus, the cover instruction may not have
the intended effect when executed by the operating system, and the
virtual monitor cannot easily trap cover instruction execution by an
operating system in order to emulate the cover instruction on behalf of
the operating system.

Spec. ¶¶ [0005]-[0006].
Appellant describes the problem succinctly in more detail:
When the Intel Itanium cover instruction runs at privilege
level 0, with the PSR register field ic set to 0, the cover instruction
copies the current contents of the CFM register to CR[IFS].ifm, but
when the cover instruction runs at a less-privileged privilege level of
1, 2, or 3, with the PSR register field ic is set to 1, the cover
instruction does not copy the current contents of the CFM register to
CR[IFS].ifm. In other words, execution of the cover instruction
behaves quite differently depending on the processor state at the time
at which the cover instruction is executed.

The basic problem with the cover instruction for a virtual
monitor is that the virtual monitor, rather than the operating system,
runs at privilege level 0, and the operating system executes at a less-
privileged privilege level than privilege level 0, despite having been
designed to run a privilege level 0. When the operating system
executes a cover instruction, the operating system expects that the
cover instruction copies the current contents of the CFM register to
CR[IFS].ifm. However, since the operating system is actually
executing at a less-privileged privilege level, the cover instruction
does not copy the current contents of the CFM register to
CR[IFS].ifm. Thus, the virtual monitor must emulate the privilege-
Appeal 2008-005204
Application 10/903,613

8
level-0 execution behavior of the cover instruction on behalf of the
operating system.

As described, the cover instruction is a non-privileged instruction that has
two types of execution behavior, depending upon the privilege level.
The invention determines whether the cover instruction occurred
between a "first event," an interruption or a setting of PSR.ic to zero, and a
"second event," an attempt to read CR[IFS], and, if so, the virtual monitor
emulates the contents of CR[IFS]. Spec. ¶¶ [0050]-[0051].

Eiraku
Eiraku describes:
There are two prominent approaches to running multiple
operating systems over a single hardware platform: Virtual machines
. . . and user-level operating systems . . . . Virtual machines provide
isolated execution environments for multiple operating system
kernels, which can run over the native hardware. A user-level
operating system is an operating system that runs as a regular user
process on another host operating system.

P. 2.
Eiraku proposes "a new implementation method of user-level OSes
with partial emulation of hardware and rewriting of machine instructions at
compile time." P. 2.
Eiraku states:
In our implementation method, we emulate all privileged
instructions. In addition, we emulate some non-privileged instructions
that are tightly related with the privileged instructions. It is easy to
detect execution of privileged instructions because the real CPU
throws privilege violation exceptions. However, it is not trivial to
detect execution of such non-privileged instructions.

Appeal 2008-005204
Application 10/903,613

9
To solve this problem, we use static rewriting of machine
instructions at compile-time in two ways. One way is to insert an
illegal instruction before each non-privileged instruction to be
detected. Another way is to replace privileged instructions and related
non-privileged instructions with subroutine calls for emulation.

P. 3.
Eiraku further states that "[t]he real problem on emulation is to detect
the executions of some non-privileged instructions that are tightly coupled
with corresponding privileged instructions. For example, ltr (load task
register) of IA-32 is a privileged instruction while str (store task register) is a
non-privileged instruction." P. 5. The Examiner relies solely on the method
described in section, "3.1.1 Inserting an illegal instruction" before every
non-privileged instruction is to be detected.
Eiraku describes inserting an illegal instruction before every
non-privileged instruction to be detected. P. 5. As noted, privileged
instructions are easily detected without this step.
Eiraku describes that when the user-level OS executes a privileged
instruction or an inserted illegal instruction, a partial emulator is notified and
fetches the instruction pointed to by the program counter. "If the instruction
is a privileged instruction, it is handled by the partial emulator. If the
instruction is an inserted illegal instruction, the partial emulator fetches and
handles the next instruction. After that, the partial emulator adjust the
program counter . . . ." P. 5.

ANTICIPATION

Principle of law
Appeal 2008-005204
Application 10/903,613

10
"Anticipation requires the presence in a single prior art disclosure of
all elements of a claimed invention arranged as in the claim." Connell v.
Sears, Roebuck & Co., 722 F.2d 1542, 1548 (Fed. Cir. 1983).

Issue
Since Appellant argues each limitation of claim 1, we state the issue
broadly as: Has Appellant shown error in the Examiner's finding of
anticipation of claim 1?

Analysis
We address the first three claim limitations as dispositive.
1.
Appellant argues that Eiraku does not teach "a non-privileged
computer instruction with at least two types of execution behavior,
depending on prior events and on a current privilege level." Br. 17.
The Examiner states that the limitation of "a non-privileged computer
instruction with at least two types of execution behavior, depending on prior
events and on a current privilege level" has not been given weight because it
occurs in the preamble. Ans. 17.
Appellant replies that this language is referenced in the body of the
claim and cannot simply be ignored because it occurs in the preamble.
Reply Br. 11
The body of the claim refers back to the "non-privileged computer
instruction" in the preamble. Accordingly, it was error for the Examiner to
ignore this claim limitation in the rejection. There is no teaching that the
non-privileged instruction in Eiraku has "at least two types of execution
behavior, depending on prior events and on a current privilege level." By
Appeal 2008-005204
Application 10/903,613

11
ignoring the limitation to "at least two types of execution behavior," the
Examiner renders meaningless the limitation of "a first type of execution
behavior" in the first step of the method.
Even if some non-privileged instruction in Eiraku inherently has at
least two types of execution behavior, depending on prior events and on a
current privilege level, the Examiner has not made such a finding. In any
case, there is no teaching of "virtualizing" these instructions. Appellant has
shown reversible error in the rejection. Nevertheless, we address the next
two limitations for additional reasons justifying reversal.

2.
Appellant argues that the Examiner erred in finding that Eiraku
teaches "detecting a first event that causes a first type of execution behavior
upon subsequent execution of the non-privileged instruction."
The Examiner finds that "insertion of illegal instruction, page 5 of
Eiraku is considered equivalent to the first event; the type of execution
behavior would be that the non-privileged instruction be delayed by the
amount of time required to process the illegal instruction." Final Rej. 3.
Appellant argues: (1) Eiraku inserts the illegal instruction in order to
prevent execution of the following non-privileged instruction, and the
emulator emulates the non-privileged instruction; (2) even if the
non-privileged instruction to be emulated was subsequently executed, simply
delaying execution of an instruction does not affect or change the execution
behavior of the instruction; and (3) inserting an illegal instruction does not
detect anything because it is the faulting or trapping of the illegal instruction
that causes the partial emulator to be invoked. Br. 17-18.
Appeal 2008-005204
Application 10/903,613

12
The Examiner responds that the event only causes a first type of
execution and "interprets this limitation as 'when the first event is detected, a
first type of execution is occurred.'" Ans. 18. The Examiner states that
"delaying by a certain amount of time required to process the illegal
instruction is equivalent to a first type of execution behavior." Id.
Appellant replies that the claim clearly requires that the first event
causes a first type of execution behavior when the non-privileged instruction
is subsequently executed, and a non-privileged instruction is not executed
when the first event occurs because otherwise there would be no subsequent
execution behavior. Reply Br. 14. It is argued that the Examiner's statement
that "when the first event is detected, a first type of execution is occurred"
makes "absolutely no sense whatsoever." Id.
Part of the problem is that the rejection is awkwardly phrased. We
agree with Appellant that the act of inserting an illegal instruction is clearly
not the same as the act of detecting a first event: "inserting" is not
"detecting." We think what the Examiner probably meant to say was that
detecting the inserted illegal instruction is equivalent to "detecting a first
event." This appears to be what the Examiner is referring to by "detecting"
in the paragraph bridging pages 18 to 19 of the Answer. Nevertheless, the
Examiner's reasoning is not persuasive.
As Appellant points out, the non-privileged instruction after the illegal
instruction is not "executed," but is "emulated," and therefore does not meet
the limitation of "upon subsequent execution of the non-privileged
instruction." We also agree with Appellant that even if the non-privileged
instruction was executed instead of emulated, delaying the execution of the
instruction does not affect or change the behavior of the instruction; the
Appeal 2008-005204
Application 10/903,613

13
instruction executes in the same way whenever it is called. The occurrence
of the illegal instruction is not an "event that causes a first type of execution
behavior upon subsequent execution of the non-privileged instruction,"
because it does not change the way the non-privileged instruction works, but
merely causes the processor to issue a fault or trap. Therefore, detecting an
illegal instruction is not "detecting an event that causes a first type of
execution behavior upon subsequent execution of the non-privileged
instruction." Appellant has shown clear error in the Examiner's finding as to
this limitation. We consider one more limitation.

3.
Appellant argues that the Examiner erred in finding that Eiraku
teaches "configuring a detection mechanism that detects subsequent
execution of the non-privileged instruction."
The Examiner finds that this limitation is met by Eiraku: "see e.g.
page 5, paragraph beginning with 'Since the byte sequence . . .', sentence
beginning with 'We Can detect the execution . . . . '; see also page 5, col. 1,
'To detect execution . . . . . '" Final Rej. 3.
Appellant argues that the Examiner improperly relies on the same
portion of Eiraku as for the limitation of "detecting a first event" when two
different elements are claimed. Br. 19. Appellant notes that the Examiner
appears to state that inserting the illegal instruction detects a first event that
causes a first type of execution behavior as well as configures a detection
mechanism that detects subsequent execution of a non-privileged instruction.
Id. It is argued that "a fault caused by an attempt to execute an illegal
Appeal 2008-005204
Application 10/903,613

14
instruction does not, by itself, detect a subsequent instruction. It simply
causes the processor to issue a fault or trap." Id.
The Examiner responds that the "'detection mechanism' is interpreted
to be the mechanism that is doing the detection in the first limitation [of
detecting a first event]." Ans. 20.
Appellant replies that "[t]he detection mechanism in the second
element of claim 1 detects 'subsequent execution of the non-privileged
instruction.' The detection mechanism therefore detects execution of the
non-privileged instruction that occurs subsequent to occurrence of the first
event, and cannot therefore possibly detect the first event." Reply Br. 15.
We agree with Appellant that the Examiner clearly errs in interpreting
the "detection mechanism" to be doing the detection in the step of "detecting
a first event." The limitation "detecting a first event that causes a first type
of execution behavior upon subsequent execution of the non-privileged
instruction" clearly requires detecting an event which occurs before
execution of the non-privileged instruction. The limitation of "configuring a
detection mechanism that detects subsequent execution of the non-privileged
instruction" requires detecting execution of the non-privileged instruction,
and not the earlier event. Eiraku does not describe detecting execution of
the non-privileged instruction. Accordingly, Appellant has shown error as to
the limitation.

Conclusion
Appellant has shown error in the Examiner's finding of anticipation of
claim 1. While we have discussed only three limitations, we have
considered Appellant's arguments as to the other limitations and find them
Appeal 2008-005204
Application 10/903,613

15
also to be persuasive. Accordingly, the rejection of claims 1 and 10 are
reversed.

OBVIOUSNESS
Appellant's admitted prior art does not cure the deficiencies of Eiraku
as to the rejection of claims 1 and 10. Therefore, the rejection of claims 2-9
and 11-16 is reversed.

CONCLUSION
The rejection of claims 9-16 under 35 U.S.C. § 101 is affirmed.
The rejection of claims 1 and 10 stand rejected under 35 U.S.C.
§ 102(b) over Eiraku is reversed.
The rejection of claims 2-9 and 11-16 under 35 U.S.C. § 103(a) over
Eiraku and the admitted prior art is reversed.
Requests for extensions of time are governed by 37 C.F.R. § 1.136(b).
See 37 C.F.R. § 41.50(f).

AFFIRMED-IN-PART

erc

HEWLETT-PACKARD COMPANY
Intellectual Property Administration
3404 E. Harmony Road
Mail Stop 35
FORT COLLINS, CO 80528