Ex Parte GARBACEA

Patent Trial and Appeal Board

Feb 26, 2019

13491781 (P.T.A.B. Feb. 26, 2019)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE
13/491,781
85181 7590
Adams Intellex, PLC
PO Box 197
Hinesburg, VT 05461
06/08/2012
02/28/2019
FIRST NAMED INVENTOR
Ilie GARBACEA
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
MPS-237US1 9263
EXAMINER
HUISMAN, DAVID J
ART UNIT PAPER NUMBER
2183
NOTIFICATION DATE DELIVERY MODE
02/28/2019 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
patents@adamsip.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte ILIE GARBACEA
Appeal2018-004589
Application 13/491,781 1
Technology Center 2100
Before MAHSHID D. SAADAT, JASON J. CHUNG, and
BETH Z. SHAW, Administrative Patent Judges.
CHUNG, Administrative Patent Judge.
DECISION ON APPEAL
This is a decision on appeal under 35 U.S.C. § 134(a) of the Final
Rejection of claims 1-26. We have jurisdiction under 35 U.S.C. § 6(b ).
We reverse.
INVENTION
The invention is directed to microprocessors. Spec. ,r 1. Claim 1 is
illustrative of the invention and is reproduced below:
1. A method of rescheduling threads among a
plurality of microprocessor cores of a multithreaded
microprocessor including a shared pool of physical registers,
the method comprising:
1 According to Appellant, Imagination Technologies, LLC is the real party in
interest. App. Br. 1.
Appeal2018-004589
Application 13/491,781
determining that a first instruction in a first thread to be
executed by a first microprocessor core of said multithreaded
microprocessor requires a first logical register;
determining that a second instruction in a second thread
to be executed by a second microprocessor core of said
multithreaded microprocessor requires a second logical register;
allocating a first physical register in the shared pool to
the first thread for execution of the first instruction;
mapping the first logical register to the first physical
register;
allocating a second physical register in the shared pool to
the second thread for execution of the second instruction;
mapping the second logical register to the second
physical register;
upon determining that said first thread should be
descheduled, storing contents of said first physical register to a
memory, and deallocating said first physical register from said
first thread;
upon determining that said first thread should be
rescheduled, determining whether sufficient physical registers
are available in the shared pool to support execution of said first
thread;
if sufficient physical registers in the shared pool are
available, mapping said first logical register to an available
physical register in the shared pool and loading said stored
contents of said first thread from said memory to said mapped
available physical register; and
rescheduling the first thread for execution by a third
microprocessor core of said multithreaded microprocessor.
REJECTIONS AT ISSUE
Claims 1-7, 9-17, and 19-26 stand rejected under 35 U.S.C. § 103 as
being unpatentable over the combination of Eichenberger (US
2009/0100249 Al; published Apr. 16, 2009), Nishida (US 2008/0270736
Al; published Oct. 30, 2008), Official Notice, Jiao (US 2011/0261063 Al;
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Appeal2018-004589
Application 13/491,781
published Oct. 27, 2011), and Accapadi (US 2005/0210472 Al; published
Sept. 22, 2005). Final Act. 3-11.
Claims 8 and 18 stand rejected under 35 U.S.C. § 103 as being
unpatentable over the combination of Eichenberger, Nishida, Official
Notice, Jiao, Accapadi, and Agarwal (US 6,308,252 Bl; issued Oct. 23,
2001). Final Act. 11-12.
Claims 1, 11, and 21 stand rejected under 35 U.S.C. § 103 as being
unpatentable over the combination of Nishida, Official Notice, Accapadi,
and Jiao. Final Act. 12-17.
ANALYSIS
The Examiner takes Official Notice for various claimed features as
notoriously well known in the art at the time of the invention. Final Act. 3-
7, 12-17; Ans. 6-7.
Appellant argues the Examiner improperly takes Official Notice
because the claimed features the Examiner relies on Official Notice are
within esoteric technology, which means these features must be supported
by citation to a prior art reference. App. Br. 8-9; Reply Br. 2-3. We agree
with Appellant.
At the outset, we note that the Examiner does not provide any
references to support of assertions of Official Notice to rebut Appellant's
argument. Rather, the Examiner states Appellant's traversal is inadequate.
MPEP § 2144.03(C) pertains to Official Notice and states:
To adequately traverse such a finding, an applicant must
specifically point out the supposed errors in the examiner's
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Application 13/491,781
action, which would include stating why the noticed fact is not
considered to be common knowledge or well-known in the art.
Moreover, MPEP § 2144.03(C) states:
If applicant does not traverse the examiner's assertion of official
notice or applicant's traverse is not adequate, the examiner
should clearly indicate in the next Office action that the common
knowledge or well-known in the art statement is taken to be
admitted prior art because applicant either failed to traverse the
examiner's assertion of official notice or that the traverse was
inadequate. If the traverse was inadequate, the examiner should
include an explanation as to why it was inadequate.
(Emphasis added.)
In this case, the question we must answer pertains to the degree of the
word "specifically." Put another way, we determine if Appellant reaches the
requisite level of adequate traversal by "specifically" pointing out the errors
in the Examiner's action.
We determine Appellant specifically points out the supposed errors in
the Examiner's action. In particular, Appellant argues, and we agree, the
claimed features the Examiner relies on Official Notice are within esoteric
technology, which means these features must be supported by citation to a
prior art reference. App. Br. 8-9; Reply Br. 2-3. For example, other than
speculation, the Examiner's Official Notice has not established how the
claim limitations "upon determining that said first thread should be
descheduled, storing contents of said first physical register to a memory, and
deallocating said first physical register from said first thread" and "upon
determining that said first thread should be rescheduled, determining
whether sufficient physical registers are available in the shared pool to
support execution of said first thread" involve well-known steps.
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Application 13/491,781
Accordingly, we do not sustain the Examiner rejection of:
(1) independent claims 1, 11, and 21; and (2) dependent claims 2-10, 12-20,
and 22-26.
DECISION
We reverse the Examiner's decision rejecting claims 1-26 under
35 U.S.C. § 103(a).
REVERSED
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