Ex Parte Gao et al

Patent Trial and Appeal Board

Dec 14, 2016

11531313 (P.T.A.B. Dec. 14, 2016)

United States Patent and Trademark Office
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O.Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
11/531,313 09/13/2006 Yaoqing Gao CA920060047US1 1024
46320 7590
CRGO LAW
STEVEN M. GREENBERG
7900 Glades Road
SUITE 520
BOCA RATON, EL 33434
12/16/2016 EXAMINER
SWIFT, CHARLES M
ART UNIT PAPER NUMBER
2196
NOTIFICATION DATE DELIVERY MODE
12/16/2016 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
docketing@crgolaw.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte YAOQING GAO, GHEORGHE C. CASCAVAL,
ALLAN H. KIELSTRA, ROBERT B. TREMAINE,
MICHAEL E. WAZLOWSKI, and LIXIN ZHANG
Appeal 2016-002554
Application 11/531,313
Technology Center 2100
Before JEAN R. HOMERE, JEFFREY S. SMITH, and
CATHERINE SHIANG, Administrative Patent Judges.
SMITH, Administrative Patent Judge.
DECISION ON APPEAL
Appeal 2016-002554
Application 11/531,313
STATEMENT OF THE CASE
This is an appeal under 35 U.S.C. § 134(a) from the rejection of
claims 1—40, which are all the claims pending in the application. We have
jurisdiction under 35 U.S.C. § 6(b). This application was previously before
us as Appeal 2011-009644 in which we affirmed the rejection of claims 1—
40 on February 26, 2016.
We affirm.
Illustrative Claim
1. A method of generating an application, the method
comprising:
improving access to application data for the application
in program code for the application, the improving including:
adding a push request for a memory-side data prefetch to
the program code, wherein the memory-side data prefetch
causes a near memory processor (NMP) to copy the application
data from a first data store to a second data store that is faster
than the first data store; and
adding a prefetch request for a processor-side data
prefetch to the program code, wherein
the processor-side data prefetch causes a main processor
that is different than the NMP to copy the application data from
the second data store to a third data store that is faster than the
second data store, and wherein
the push request and the prefetch request cooperate to
hide a memory access latency for the application data.
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Appeal 2016-002554
Application 11/531,313
Prior Art
Archambault et al. US 2006/0048120 A1 Mar. 2, 2006
Chia-Lin Yang et al., Push vs. Pull: Data Movement for Linked Data
Structures, International Conference on Supercomputing (ICS) 176—
86 (2000).
Examiner’s Rejections
Claims 7 and 8 stand rejected under 35U.S.C. § 112, second
paragraph as being indefinite.
Claims 1—4, 6, 7, 10-13, 15, 16, 18—21, 23—27, and 29-40 stand
rejected under 35 U.S.C. § 102(b) as anticipated by Yang.
Claims 5, 9, 14, 17, 22, and 28 are rejected under 35 U.S.C. § 103(a)
as unpatentable over Yang and Archambault.
ANALYSIS
We adopt the findings of fact made by the Examiner in the Final
Action and Examiner’s Answer as our own. We concur with the conclusions
reached by the Examiner for the reasons given in the Examiner’s Answer.
We highlight the following for emphasis.
Appellants do not respond to the Examiner’s rejection of claims 7 and
8 under 35 U.S.C. § 112, second paragraph, which we summarily affirm.
Appellants contend Yang does not disclose “adding a push request for
a memory-side data prefetch to the program code” as claimed. App. Br. 6—
12. The Examiner finds the claimed push request is disclosed by Yang in
describing a cache miss signal passed from L2 prefetch engine to memory
level prefetch engine as shown in Figure 3, where the memory level prefetch
engine, in response to the cache miss signal, pushes data from main memory
to L2. Ans. 19. Appellants respond that a cache miss signal described by
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Appeal 2016-002554
Application 11/531,313
Yang is not a request, because the cache miss signal does not instruct the
computer to perform another function. Reply Br. 6.
Appellants’ contention appears based on a difference in terminology,
namely, that the claim term “push request” is not described by the prior art
word “signal.” However, anticipation “is not an ‘ipsissimis verbis’ test.” In
re Bond, 910 F.2d 831, 832 (Fed. Cir. 1990) (citing Akzo N.V. v. United
States Inti Trade Comm’n, 808 F.2d 1471, 1479 &n.ll (Fed. Cir. 1986)).
“An anticipatory reference . . . need not duplicate word for word what is in
the claims.” Standard Havens Prods, v. Gencor Indus., 953 F.2d 1360, 1369
(Fed. Cir. 1991).
Appellants have not provided a definition of “push request” that
excludes a prefetch engine receiving a cache miss signal and, as a result of
receiving the cache miss signal, subsequently pushing data from main
memory to L2 as described by Yang. Appellants do not persuasively rebut
the Examiner’s finding that the claim limitation “adding a push request for a
memory-side data prefetch to the program code” is disclosed by Yang in
describing a cache miss signal results in data being pushed from main
memory to L2.
We sustain the rejection of claim 1 under 35 U.S.C. § 102. Appellants
do not present arguments for separate patentability of claims 2 40, which
fall with claim 1.
DECISION
The Examiner’s rejections of claims 1—40 are affirmed.
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Appeal 2016-002554
Application 11/531,313
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a). See 37 C.F.R.
§ 41.50(f).
AFFIRMED
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