Ex Parte Galles et al

Patent Trial and Appeal Board

Apr 25, 2014

10696146 (P.T.A.B. Apr. 25, 2014)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
10/696,146 10/29/2003 Michael B. Galles SGI-048COA 5506
113552 7590 04/28/2014
Lewis Roca Rothgerber LLP- SGI
2440 W. El Camino Real
6th Floor
Mountain View, CA 94040
EXAMINER
TREAT, WILLIAM M
ART UNIT PAPER NUMBER
2183
MAIL DATE DELIVERY MODE
04/28/2014 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)

UNITED STATES PATENT AND TRADEMARK OFFICE
________________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
________________

Ex parte MICHAEL B. GALLES and
JEFFREY S. KUSKIN1
________________

Appeal 2011-011393
Application 10/696,146
Technology Center 2100
________________

Before CAROLYN D. THOMAS, ELENI MANTIS MERCADER, and
JASON V. MORGAN, Administrative Patent Judges.

MORGAN, Administrative Patent Judge.

DECISION ON APPEAL
Introduction
This is an appeal under 35 U.S.C. § 134(a) from the Examiner’s Non-
Final Rejection of claims 1-20. We have jurisdiction under 35 U.S.C.
§ 6(b).
We AFFIRM.

1 Silicon Graphics, Inc., is the Real Party in Interest. App. Br. 2.
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Invention
Appellants invented a multi-processor system that includes a plurality
of processors. Abstract. “Each of the plurality of processors 12 has a
memory 16, a memory directory 18, and a central processing unit 20 all
integrated into a single device.” Spec. 7:5-7.
Exemplary Claim
Claim 1, reproduced below with key limitations emphasized, is
representative:
1. A multi-processor system, comprising:
a plurality of processors, each processor including an
integrated memory operable to provide/receive/store data, each
processor including a central processing unit having an
integrated memory controller operable to control access to the
integrated memory and an integrated memory directory
operable to maintain a plurality of memory references to data
within the integrated memory and at least one memory
reference to data within an integrated memory of a different
processor;
an external switch coupled to each of the plurality of
processors, the external switch operable to pass data to and
from any of the plurality of processors, the external switch
including an external directory, the external directory operable
to provide a memory reference for each of the plurality of
processors to remote data that is not provided within its own
integrated memory directory.
Rejections
The Examiner rejects claims 1-10 and 16-20 under 35 U.S.C. § 112,
first paragraph, as failing to comply with the written description
requirement. Ans. 10-13.
The Examiner rejects claims 1-20 under 35 U.S.C. § 112, second
paragraph, as being indefinite for failing to particularly point out and
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distinctly claim the subject matter which Appellants regard as the invention.
Ans. 3-9.
The Examiner rejects claims 11-15 under 35 U.S.C. § 102(b) as being
anticipated by Kabemoto (U.S. 5,890,217; Mar. 30, 1999). Ans. 13-18.
The Examiner rejects claims 1, 4-17, and 19 under 35 U.S.C. § 103(a)
as being unpatentable over Janakiraman (U.S. 6,374,331 B1; Apr. 16,
2002).2 Ans. 19-27.
The Examiner rejects claims 2, 3, 18, and 20 under 35 U.S.C. § 103(a)
as being unpatentable over Janakiraman and Anoop Gupta et al., Reducing
Memory and Traffic Requirements for Scalable Directory-Based Cache
Coherence Schemes, PROC. INT’L CONF. ON PARALLEL PROCESSING (Aug.
1990). Ans. 28-29.
OBJECTIONS
In addition to the above rejections, the Examiner objects to
amendments to the Specification under 35 U.S.C. § 132(a). Ans. 10-12.
Ordinarily, an objection is reviewable by petition under 37 C.F.R. § 1.181
and a rejection is appealable to the Patent Trial and Appeal Board. When
the issue of new matter presented is the subject of both an objection and a
rejection, the issue is appealable. MPEP § 2163.06(II) (9th ed., Mar. 2014);
see also id. § 608.04(c) (“[W]here the alleged new matter is introduced into
or affects the claims, thus necessitating their rejection on this ground, the

2 The Examiner lists claims 1-20 as being rejected under 35 U.S.C. § 103(a)
as being unpatentable over Janakiraman alone, but does not otherwise
address claims 2, 3, 18, and 20 under this rejection. However, because the
Examiner rejects these claims under 35 U.S.C. § 103(a) as being
unpatentable over Janakiraman and Gupta, this typographical error does not
affect the outcome of this case.
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question becomes an appealable one, and should not be considered on
petition even though that new matter has been introduced into the
specification also.”). Our decision with respect to the 35 U.S.C. § 112, first
paragraph, rejection is dispositive to this objection to the extent that the
objection and rejection turn on the same issues.
The Examiner further objects to the drawings as failing to comply
with 37 C.F.R. § 1.84(p)(5) (“Reference characters not mentioned in the
description shall not appear in the drawings. Reference characters
mentioned in the description must appear in the drawings”). Ans. 12-13.
The Examiner finds there are “inconsistencies between the specification and
Fig. 2 noted in the 35 USC 112, 2nd rejection.” Id. at 12. The purported
reference character discrepancies to which the Examiner refers relate to the
Specification as it stood before Appellants’ objected-to amendments. Id. at
4-7. Importantly, the Examiner does not identify any reference character
discrepancies between the drawings and the Specification as amended.3 Id.
Thus, the Examiner’s reference character discrepancies objection depends on
the Examiner’s new matter objection. Therefore, our decision with respect
to the 35 U.S.C. § 112, first paragraph, rejection is also dispositive to this
second objection to the extent that the objection and rejection turn on the
same issues.

3 The Examiner correctly notes that Figure 2 identifies a “Bus Controller” as
element 34 even though the Specification, even as amended, identifies this
element as a “CPU Controller.” Ans. 6. However, the label for element 34
is not a reference character; thus, this discrepancy does not form a basis for
the Examiner’s objection to the drawings due to purported reference
character discrepancies. Id. at 12-13; 37 C.F.R. § 1.84(p)(5). In the event of
further prosecution, the Examiner should ascertain whether this label
discrepancy necessitates a separate objection.
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ISSUES
1. Did the Examiner err in finding that Figure 2 of Appellants’
Specification illustrates a processor having a memory and a CPU rather than
a CPU within a processor?
2. Did the Examiner err in finding Kabemoto discloses: (1) a “local
memory being integrated within a particular one of a plurality of processors”
and (2) “a memory directory integrated with a central processing unit of the
particular one of the plurality of processors,” as recited in claim 11?
3. Did the Examiner err in finding Janakiraman teaches or suggests:
(1) “a central processing unit having an integrated memory controller
operable to control access to the integrated memory” and (2) “an integrated
memory directory operable to maintain a plurality of memory references to
data within the integrated memory,” as recited in claim 1?
ANALYSIS
Claims 1-10 and 16-20 (35 U.S.C. § 112, first paragraph)
The Examiner rejects claims 1 under 35 U.S.C. § 112, first paragraph,
because the Examiner “is unable to find, in applicants’ original written
description, support for the claim language in claim 1 reciting ‘a central
processing unit having an integrated memory controller operable to control
access to the integrated memory[’] . . . .” Ans. 10 (emphasis added).
Specifically, the Examiner finds “[t]here is nothing supporting the claim to
the CPU [(central processing unit)] having such a memory controller though
there is support for the processor having such a controller.” Id.
Appellants argue, “FIGURE 2 is a detailed view of CPU 20 within
processor 12. Accordingly, memory controller 30 and memory directory 18
are clearly shown to be within central processing unit 20.” App. Br. 11.
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However, the Examiner disagrees that Figure 2 illustrates a CPU; the
Examiner instead finds, “Fig. 2 is an embodiment of a processor within the
multiprocessor system.” Ans. 5. Consequently, the Examiner also: (1)
objects to amendments to the Specification (May 23, 2006, and October 6,
2006) that describe Figure 2 as illustrating CPU 20, rather than processor 12,
id. at 5-6, 10-11; and (2) objects to Figure 2 because it is inconsistent with
the Specification absent the objected-to amendments, id. at 12-13. In other
words, the Examiner finds that Figure 2 of the Specification, rather than the
Specification’s description of Figure 2, has errors. Therefore, the Examiner
finds Figure 2 cannot provide the written descriptive support for the claimed
invention.
We disagree with the Examiner’s findings and conclusions.
“[D]rawings alone may provide a ‘written description’ of an invention as
required by § 112.” See Vas-Cath Inc. v. Mahurkar, 935 F.2d 1555, 1565
(Fed. Cir. 1991). Here, Figures 1 and 2 have multiple features that
persuasively show that Figure 2 illustrates CPU 20 rather than processor 12.
Figure 1 is reproduced below:

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Figure 1 depicts, among other things, processor 12 having within it
memory 16 connected to CPU 20, CPU 20 having within it directory 18.
Figure 2 is illustrated below:

Figure 2 depicts a box 20 having within it, among other things,
memory controller 30 and directory 18. A double-sided arrow labeled
“TO/FROM MEMORY” is connected to box 20.
The re-use of reference number 20, the existence of directory 18
within both CPU 20 in Figure 1 and box 20 in Figure 2, and the connection
to/from memory shown outside box 20 in Figure 2, but shown (unlabeled)
inside processor 12 in Figure 1, together provide persuasive support for
Appellants’ argument that Figure 2 is correct to the extent that it depicts a
CPU. App. Br. 11.
In response to Appellants’ arguments, the Examiner first notes
Appellants “never submitted a proposed drawing change to change the ‘Bus
Controller’ legend to ‘CPU Controller’ for element 34 of Fig. 2.” Ans. 6.
This discrepancy is confusing, and Appellants do not address it in the Briefs.
However, the Examiner provides no explanation as to how the label “Bus
Controller” demonstrates Figure 2 illustrates a processor having within it a
CPU rather than CPU 20. Thus, this discrepancy by itself is insufficient to
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outweigh the ample evidence, described above, showing that Figure 2 of the
Specification depicts a CPU.
The Examiner, referring to parent application 09/418,520, further
notes Appellants “never sought to file a Certificate of Correction that would
make the issued patent consistent in scope with the changes they propose for
the child application.” Id. However, the parent application is not before us
and we will not weigh in on whether it is correct. Thus, the Examiner’s
findings with respect to the parent application and the patent that issued
therefrom do not persuade us Figure 2 is erroneous and the amendments to
the Specification constitute new matter.
The Examiner also finds “[w]ere applicants inclined to see Fig. 2 as a
drawing of an embodiment of a processor, the examiner is sure they would
argue the 18 was a typo and should have been a 12.” Id. at 11. However,
the Examiner does not identify any instance in which Appellants made such
an argument. The Examiner’s speculation as to Appellants’ arguments in
this counterfactual situation is not evidence; such speculation does not
persuade us that Figure 2 is erroneous and the amendments to the
Specification constitute new matter.
Based on the preponderance of evidence, we agree with Appellants
the Examiner erred in finding that Figure 2 of Appellants’ Specification
illustrates a processor having a memory and a CPU rather than a CPU within
a processor. App. Br. 11. Accordingly, we do not sustain the Examiner’s 35
U.S.C. § 112, first paragraph, rejection of claim 1, and of claims 2-10 and
16-20, which are similarly rejected.
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Claims 1-10 and 16-20 (35 U.S.C. § 112, second paragraph)
The Examiner rejects claims 1 under 35 U.S.C. § 112, second
paragraph, because the Examiner finds “[t]he scope of applicants’ original
disclosure does not support the claim language of independent claim[] 1 . . .
requiring, in substance, a CPU have a memory controller, as in claim 1 . . . .”
Ans. 7 (emphasis added). Thus, the Examiner concludes the scope of claim
1 is ambiguous, rendering claim 1 indefinite.
The basis of this rejection is the Examiner’s finding that Figure 2 of
Appellants’ Specification illustrates a processor having a memory and a
CPU rather than a CPU within a processor. As discussed above, this finding
is erroneous. Therefore, we agree with Appellants that the Specification
discloses, and thus renders definite, the disputed recitations. App. Br. 8-9.
Accordingly, we do not sustain this 35 U.S.C. § 112, second
paragraph, rejection of claim 1, or of claims 2-10 and 16-20, which are
similarly rejected.
Claims 1-20 (35 U.S.C. § 112, second paragraph)
The Examiner further rejects claims 1-20 under 35 U.S.C. § 112,
second paragraph, because the Examiner finds the term “integrated”
ambiguous as “[t]here is nothing in their original specification that describes
whether the CPU (20) and the memory controller (30) represent two boards,
two chips, etc. or describes that the memory controller is part of the CPU.”
Ans. 8 (emphasis added).
Again, the basis of this rejection is the Examiner’s finding that Figure
2 of Appellants’ Specification illustrates a processor having a memory and a
CPU rather than a CPU within a processor. As discussed above, this finding
is erroneous. Moreover, the Figure 2 depiction of memory controller 30
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inside CPU 20 is consistent with the Specification’s description of integrated
to refer to multiple components that are all part of a single device. Spec.
7:5-7. Therefore, we agree with Appellants that the Specification discloses,
and thus renders definite, the disputed recitations. App. Br. 10.
Accordingly, we do not sustain this 35 U.S.C. § 112, second
paragraph, rejection of claim 1, or of claims 2-20, which are similarly
rejected.
Claims 11-15 (35 U.S.C. § 102(b))
The Examiner finds that Kabemoto’s local storage 28, found within
each processor module 10-1 to 10-5, discloses a “local memory being
integrated within a particular one of a plurality of processors.” Ans. 14.
Appellants contend the Examiner erred because “local memory 28 of . . .
Kabemoto . . . is shown to be associated with, but separate and apart from,
its four processor elements 14-1 to 14-4.” App. Br. 15 (emphasis added);
see also Reply Br. 6.
Appellants’ arguments are not responsive to the Examiner’s finding
that local memory 28 is part of each processor module 10-1 to 10-5. Ans.
14. Moreover, Appellants do not persuasively distinguish between the
processor modules of Kabemoto and the claimed processor. As the
Examiner correctly finds, the claims and Specification merely assign the
name “processor” “to a device with the same functionality Kabemoto
teaches though Kabemoto . . . give[s] the device another name.” Id.
Therefore, we agree with the Examiner that Kabemoto discloses a “local
memory being integrated within a particular one of a plurality of
processors,” as recited in claim 11. Id.
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The Examiner further finds Kabemoto’s disclosure of memory
directory 30, which is found within each processor module 10-1 to 10-5
along with CPU 34, discloses “a memory directory integrated with a central
processing unit of the particular one of the plurality of processors,” as
recited in claim 11. Ans. 14-15. Appellants contend the Examiner erred
because Kabemoto’s “directory memory 30 is disclosed as being associated
with, but separate and apart from, four processor elements 14-1 to 14-4 and
their respective CPUs 34.” App. Br. 15. Appellants further note
Kabemoto’s memory directory 30 “cannot directly communicate with its
processing element 14-1 and processor 16-1 with CPU 34 as the directory
memory 30 is associated with a separate memory control module 25.” Reply
Br. 5-6.
Appellants’ arguments are commensurate with the scope of the
claimed invention and therefore are not persuasive of error. Specifically,
claim 11 merely recites a memory directory that is “integrated with a central
processing unit . . . ” (emphasis added). There is nothing in claim 11
requiring the memory directory be part of or even juxtaposed with the
central processing unit. Furthermore, there is nothing in claim 11 requiring
that the memory directory be capable of directly communicating with the
central processing unit without any intermediary. We agree with the
Examiner; it is sufficient that Kabemoto depicts the memory directory
working with CPU 34 as part of the same device (i.e., the same processor
element). Ans. 15. The Examiner’s interpretation of “integrated” is
reasonable in light of the Specification’s broad description. See, e.g., Spec.
7:5-7 (Various components are integrated into a single device.). Therefore,
we agree with the Examiner that Kabemoto discloses “a memory directory
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integrated with a central processing unit of the particular one of the plurality
of processors,” as recited in claim 11.
Accordingly, we sustain the Examiner’s 35 U.S.C. § 102(b) rejection
of claim 11, and of claims 12-15, which Appellants do not argue separately
with respect to this issue. App. Br. 16.
Claims 1-20 (35 U.S.C. § 103(a))
The Examiner finds Janakiraman’s disclosure of processor chip
2500—with memory controller 2520 and processor 2540 integrated
thereon—teaches or suggests “a central processing unit having an integrated
memory controller operable to control access to the integrated memory,” as
recited in claim 1. Ans. 19-20 (citing, e.g., Janakiraman Fig. 8). Appellants
contend the Examiner erred because Janakiraman “shows a memory
controller 2520 separate from its processor 2540.” App. Br. 17; see also
Reply Br. 6-7.
Appellants’ arguments are not commensurate with the scope of claim
1 and therefore are not persuasive of error. A reasonably broad
interpretation, in light of the Specification, of “a central processing unit
having an integrated memory controller” encompasses a central processing
unit integrated with a memory controller to work together as part of a single
device. Cf. In re Larson, 340 F.2d 965, 967 (CCPA 1965) (The term
“integral” includes various means of maintaining parts fixed together as a
single unit.). In Janakiraman, a single device, processor chip 2540, fixes
together both memory controller 2520 and processor 2540. Janakiraman
Fig. 8. Memory controller 2520 and processor 2540 work together through
their connections to memory controller 2530. Id. col. 8, ll. 20-24.
Therefore, we agree with the Examiner Janakiraman teaches or suggests “a
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central processing unit having an integrated memory controller operable to
control access to the integrated memory,” as recited in claim 1. Ans. 19-20.
The Examiner acknowledges Janakiraman does not explicitly disclose
a directory cache incorporated into a processor chip with a local memory.
Ans. 20. However, the Examiner correctly finds Janakiraman teaches the
use of directory caches, id. at 19 (citing Janakiraman Fig. 7), and finds “one
of ordinary skill would recognize that the information provided by a
directory cache . . . is still useful in a system with the local memory and
memory controller incorporated into the processor chip,” Ans. 20.
Janakiraman’s teaching that directory caches enable the supply of memory
data “to the associated processor as soon as the directory cache indicates the
data is valid without waiting for the response from the coherence controller
at the communication switch” supports the Examiner’s findings.
Janakiraman col. 7, ll. 57-61; see also Ans. 19.
Appellants further argue Janakiraman teaches away from integrating
the memory directory, as claimed, by stating “that it is not desirable to locate
the coherence control on the processor chip collocated with the memory
controller.” App. Br. 18 (citing Janakiraman col. 8, ll. 29-35). However, the
teaching to which Appellants refer relates to whether it is desirable to locate
coherence controller 6000 on the processor chip. Janakiraman col. 8, ll. 22-
25, 29-32; Figs. 7, 8. The Examiner’s findings relate to whether it would
have been obvious to an artisan of ordinary skill to incorporate a directory
cache 2100 into a processor chip. Ans. 20. Thus, Appellants’ arguments are
not responsive to the Examiner’s findings and are not persuasive of error.
Therefore, we agree with the Examiner that Janakiraman teaches or suggests
“an integrated memory directory operable to maintain a plurality of memory
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references to data within the integrated memory,” as recited in claim 1. Ans.
19-21.
Accordingly, we sustain the Examiner’s 35 U.S.C. § 103(a) rejection
of claim 1, and of claims 2-20, which Appellants do not argue separately
with respect to this issue. App. Br. 18-20.
DECISION
We reverse the Examiner’s rejection of claims 1-10 and 16-20 under
35 U.S.C. § 112, first paragraph.
We reverse the Examiner’s rejections of claims 1-20 under 35 U.S.C.
§ 112, second paragraph.
We affirm the Examiner’s rejection of claims 11-15 under 35 U.S.C.
§ 102(b).
We affirm the Examiner’s rejections of claims 1-20 under 35 U.S.C.
§ 103(a).
Because we affirm at least one of the Examiner’s rejections for each
of claims 1-20, we affirm the Examiner’s decision to reject claims 1-20.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a). See 37 C.F.R.
§ 41.50(f).

AFFIRMED

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