Ex Parte Gaither et al

Patent Trial and Appeal Board

Sep 17, 2013

11635316 (P.T.A.B. Sep. 17, 2013)

UNITED STATES PATENT AND TRADEMARK OFFICE
_____________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
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Ex parte BLAINE D. GAITHER and VERNA KNAPP
_____________

Appeal 2011-001220
Application 11/635,316
Technology Center 2100
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Before, JOSEPH F. RUGGIERO, DAVID M. KOHUT, and
BRYAN F. MOORE, Administrative Patent Judges.

KOHUT, Administrative Patent Judge.

DECISION ON APPEAL

Appeal 2011-001220
Application 11/635,316

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This is a decision on appeal under 35 U.S.C. § 134(a) of the Final
Rejection of claims 1-17, 19, 20, and 22-26.1 We have jurisdiction under 35
U.S.C. § 6(b).
We affirm-in-part the Examiner’s rejection of these claims.

INVENTION
The invention is directed to a method, computer-readable medium,
apparatus, and system for handling storage requests on a serial fabric. Spec.
2. Claim 1 is representative of the invention and is reproduced below:
1. A apparatus comprising:
an interface implemented at least partly in hardware and
configured for handling a request for storage on a serial fabric,
comprising:
an address handler configured to communicate an address
on a serial line of the serial fabric, the address comprising a
plurality of fields including a field comprising at least one set
selection bit and a field comprising at least one tag bit, the
address handler configured to communicate the address on the
serial line with the field comprising at least one set selection bit
being communicated first.

REFERENCES
Rao US 5,950,219 Sep. 7, 1999

Argade US 6,223,255 B1 Apr. 24, 2001

Gaither US 6,721,848 B2 Apr. 13, 2004

Evans US 6,966,017 B2 Nov. 15, 2005

1 Claims 18 and 21 were previously cancelled.
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Vinogradov US 7,155,554 B2 Dec. 26, 2006
(filed Nov. 2, 2004)

REJECTIONS AT ISSUE
Claims 1, 4, 6, 8, 9, 14-17, 19, 22-24, and 26 are rejected under 35
U.S.C. § 103(a) as being unpatentable over the combination of Gaither and
Rao. Ans. 4-10.
Claims 2 and 12 are rejected under 35 U.S.C. § 103(a) as being
unpatentable over the combination of Gaither, Rao, and Evans. Ans. 10-12.
Claims 3 and 13 are rejected under 35 U.S.C. § 103(a) as being
unpatentable over the combination of Gaither, Rao, and Vinogradov. Ans.
12-13.
Claims 5, 7, 10, and 11 are rejected under 35 U.S.C. § 103(a) as being
unpatentable over the combination of Gaither, Rao, and Argade. Ans. 13-
16.
Claims 20 and 25 are rejected under 35 U.S.C. § 103(a) as being
unpatentable over the combination of Gaither, Rao, Evans, Vinogradov, and
Argade. Ans. 16-19.

ISSUES
Did the Examiner err in finding the combination of Gaither and Rao
teaches or suggests: “an address handler configured to communicate an
address on a serial line of the serial fabric . . . [wherein] the field comprising
at least one set selection bit being communicated first,” as recited in claim
1?
Did the Examiner err in concluding that it would have been obvious to
one of ordinary skill in the art to combine Gaither and Rao?
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Did the Examiner err in finding the combination of Gaither, Rao, and
Vinogradov teaches or suggests “wherein the address handler is configured
to communicate the address on the serial line in a plurality of fabric cycles,”
as recited in claim 3?
Did the Examiner err in finding the combination of Gaither, Rao, and
Argade teaches or suggests “wherein the address handler is configured to
communicate the address on the serial line in sequence in a bit order of the at
least one set selection bit, the at least one tag bit, and the at least one line
offset bit,” as recited in claim 5?

ANALYSIS
We have reviewed the Examiner’s rejections in light of Appellants’
contentions that the Examiner has erred.
We disagree with Appellants’ conclusions. We adopt as our own
(1) the findings and reasons set forth by the Examiner in the action from
which this appeal is taken and (2) the reasons set forth by the Examiner in
the Examiner’s rejection of the claims and in the Examiner’s Answer in
response to Appellants’ Appeal Brief. We concur with the conclusions
reached by the Examiner. In addition, below we highlight the following
arguments for emphasis.
Claims 1, 4, 6, and 8.
Appellants select claim 1 as representative of the group comprising
claims 1, 4, 6, and 8. App. Br. 7. Claim 1 requires an address handler that is
configured to communicate an address on a serial line of a serial fabric
wherein at least one set selection bit is communicated first. Appellants
argue that the combination of Gaither and Rao does not teach this limitation.
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App. Br. 7; Reply Br. 1-2. Specifically, Appellants argue that Gaither does
not teach an address handler that communicates on a serial line of a serial
fabric and Rao does not teach communicating at least one selection bit first.
App. Br. 7; Reply Br. 1-3. However, the Examiner does not cite to Gaither
or Rao to teach the limitations argued by Appellants. Instead, the Examiner
finds just the opposite. Ans. 20. The Examiner finds that Rao teaches an
address handler that communicates on a serial fabric and Gaither teaches a
set selection bit as a first input. Ans. 20. Therefore, Appellants do not
address the Examiner’s specific findings. Additionally, we agree with the
Examiner that the references teach the disputed limitation
In response, Appellants contend that Gaither teaches away from the
claimed invention because Gaither’s comparator inputs are over separate
input lines. Reply Br. 2. Appellants additionally argue that the combination
of the references “makes no technical sense” because inputting addresses
serially into a comparator would render Gaither’s system inoperative for its
intended purpose. App. Br. 9. Thus, Appellants contend that it would not
have been obvious to combine the references. Reply Br. 3. We disagree.
The Examiner is not bodily incorporating the Gaither reference into
the Rao reference. The Examiner is simply making a finding that it was
known in the art to input a set selection bit into a system as the first input, as
shown in Gaither. Ans. 20. Additionally, the Examiner finds that it was
known in the art to communicate addresses serially. Ans. 20. Therefore, we
agree with the Examiner (Ans. 20) and we consider combining Gaither’s
order with Rao’s serial communication (Ans.4-5) as nothing more than
combining familiar elements according to known methods in order to yield
predictable results. See KSR International Co. v. Teleflex Inc. 550 U.S. 398,
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416 (2007). As such, we agree with the Examiner (Ans. 4-5) and we find
that the combination yields the predictable result of optimizing memory
latency.
Thus, for the reasons mentioned supra, we sustain the Examiner’s
rejection of claims 1, 4, 6, and 8.
Claims 3 and 13.2
Appellants make the same arguments with respect to claims 3 and 13
as with respect to claim 1. App. Br. 13. Appellants additionally argue that
none of the references teach or suggest communicating an address over a
serial line in a plurality of fabric cycles because Vinogradov teaches requests
that send both the command and address annotations in one clock cycle, not
multiple. App. Br. 14. The Examiner finds that while Vinogradov does
teach that which Appellants contend, in another embodiment Vinogradov
teaches requests that are sent in two clock cycles as can be seen in column
10, lines 50-52. Ans. 23. We disagree with the Examiner.
The portion of Vinogradov cited by the Examiner merely indicates
that multiple clock cycles can be used to send commands. See Vinogradov,
col. 10, ll. 50-52. There is nothing in this portion of the reference or in the
Examiner’s Answer that indicates that the commands can be broken up and
sent in different clock cycles, as required by the claim. Thus, we cannot
sustain the Examiner’s findings with respect to claims 3 and 13.

2 We select claim 3 as representative of the group comprising claims 3 and
13 as Appellants have not argued claim 13 with particularity. 37 C.F.R.
§ 41.37(c)(1)(vii).
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Claims 5 and 11.3
Appellants make the same arguments with respect to claims 5 and 11
as with respect to claim 1. App. Br. 15. Appellants additionally argue that
none of the references teach or suggest “a bit order of at least one set
selection bit, at least one tag bit, and at least one line offset bit,” as required
by claim 5, because the sequence in Argade is a tag, index, and block offset.
App. Br. 15. The Examiner cites to a portion of Argade (Ans. 24) but fails
to show, nor do we find, how the reference relates to the claim limitations.
As such, we cannot sustain the Examiner’s rejection of claims 5 and 11.
Claims 2, 7, 9, 10, 12, 14-17, 19, 20, and 22-26.
Appellants make the same arguments with respect to claims 2, 7, 9,
10, 12, 14-17, 19, 20, and 22-26 as with respect to claim 1. App. Br. 10-13
and 16-17. Therefore, we sustain the Examiner’s rejection of these claims
for the same reasons discussed supra with respect to claim 1.

CONCLUSION4
The Examiner did not err in finding the combination of Gaither and
Rao teaches or suggests: “an address handler configured to communicate an

3 We select claim 5 as representative of the group comprising claims 5 and
11 as Appellants have not argued claim 11 with particularity. 37 C.F.R.
§ 41.37(c)(1)(vii).
4 We have decided the Appeal before us, however, in the event of further
prosecution, the Examiner should evaluate claims 22 and 26 in light of In re
Nuijten, 500 F.3d 1346 (Fed. Cir. 2007), Subject Matter Eligibility of
Computer Readable Media, 1351 Off. Gaz. Pat. Office 212 (Feb. 23, 2010),
and our recent decision in Ex parte Mewherter, 2012-007692, 2013 WL
4477509 (PTAB May 8, 2013) (precedential). We note that Appellants’
Specification specifically includes a propagation signal as a computer-
readable medium. Spec. ¶ [0033].
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address on a serial line of the serial fabric . . . [wherein] the field comprising
at least one set selection bit being communicated first,” as recited in claim 1.
The Examiner did not err in concluding that it would have been
obvious to one of ordinary skill in the art to combine Gaither and Rao.
The Examiner erred in finding the combination of Gaither, Rao, and
Vinogradov teaches or suggests “wherein the address handler is configured
to communicate the address on the serial line in a plurality of fabric cycles,”
as recited in claim 3.
The Examiner erred in finding the combination of Gaither, Rao, and
Argade teaches or suggests “wherein the address handler is configured to
communicate the address on the serial line in sequence in a bit order of the at
least one set selection bit, the at least one tag bit, and the at least one line
offset bit,” as recited in claim 5.

SUMMARY
The Examiner’s decision to reject claims 1, 2, 4, 6-10, 12, 14-17, 19,
20, and 22-26 is affirmed and the Examiner’s decision to reject claims 3, 5,
11, and 13 is reversed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).
AFFIRMED-IN-PART

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