Ex Parte Gaiarsa et alDownload PDFPatent Trial and Appeal BoardFeb 28, 201713649762 (P.T.A.B. Feb. 28, 2017) Copy Citation United States Patent and Trademark Office UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O.Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 40101/21301(2011.001) 3701 EXAMINER CLEARY, THOMAS J ART UNIT PAPER NUMBER 2185 MAIL DATE DELIVERY MODE 13/649,762 10/11/2012 30636 7590 03/01/2017 FAY KAPLUN & MARCIN, LLP 150 BROADWAY, SUITE 702 NEW YORK, NY 10038 Andrew GAIARSA 03/01/2017 PAPER Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE BEFORE THE PATENT TRIAL AND APPEAL BOARD Ex parte ANDREW GAIARSA, MAARTEN KONING, and FELIX BURTON Appeal 2016-006494 Application 13/649,762 Technology Center 2100 Before ST. JOHN COURTENAY III, LINZY T. McCARTNEY, and ALEX S. YAP, Administrative Patent Judges. COURTENAY, Administrative Patent Judge. DECISION ON APPEAL STATEMENT OF THE CASE This is an appeal under 35 U.S.C. § 134(a) from the Examiner’s Final Rejection of claims 1—3 and 5—20, which are all the claims remaining in the application. Claim 4 is cancelled. We have jurisdiction under 35 U.S.C. § 6(b). We affirm. Invention The disclosed and claimed invention on appeal “relate[s] to systems and methods for operating system aware low latency handling.” (Abstract). Appeal 2016-006494 Application 13/649,762 Representative Claim 1. A non-transitory computer readable storage medium including a set of instructions executable by a processor, the set of instructions, when executed, results in a performance of the following: receiving a fast interrupt request asserted by a hardware device while the processor is executing within a kernel critical section; executing a fast interrupt handler at a first priority level; masking out a second priority level interrupt, by an operating system primitive, before the processor enters the kernel critical section; [L] raising the second priority level interrupt by the fast interrupt handler based on the fast interrupt request, wherein the second priority level interrupt invokes a kernel service; deferring invocation of the operating system primitive for the second priority level interrupt to avoid invoking the kernel service for the second priority level interrupt until after the processor has exited the kernel critical section; and processing the second priority level interrupt once the processor has executed the kernel critical section. (Contested limitation L emphasized). Rejection Claims 1—3 and 5—20 are rejected under pre-AIA 35 U.S.C. § 103(a) as being unpatentable over the combined teachings and suggestions of two non-patent references: “AT91RM9200 FIQ FAQ and simple Example code/patch” from https://warmcat.eom/2007/09/17/at91rm9200-fiq-faq-and- 2 Appeal 2016-006494 Application 13/649,762 simple-example-code-patch.litml, (Sept. 17, 2007), website last visited February 21, 2017 (hereinafter “Warmcat”) in view of Ralph Moore, “Deferred Interrupt Processing” Micro Digital, Inc. 2005, (hereinafter “Moore”). Grouping of Claims Based upon Appellants’ arguments, we decide the appeal of all rejected claims on the basis of representative claim 1. To the extent Appellants have not advanced separate, substantive arguments for particular claims or issues, such arguments are considered waived. See 37 C.F.R. § 41.37(c)(l)(iv). ANALYSIS We have considered all of Appellants’ arguments and any evidence presented. We find Appellants’ arguments unpersuasive for the reasons discussed infra. We adopt as our own: (1) the findings and legal conclusions set forth by the Examiner in the Final Office Action (7—10) from which this appeal is taken, and (2) the findings, legal conclusions, and explanations set forth in the Answer in response to Appellants’ arguments (Ans. 8—12). We highlight and address specific findings and arguments for emphasis in our analysis below. ISSUE For each independent claim 1, 9, and 14 on appeal, Appellants contest identically recited limitation L. (App. Br. 4—8). Issue: Under § 103(a), did the Examiner err by finding the cited combination of Warmcat and Moore would have taught or suggested limitation L: “raising the second priority level interrupt by the fast interrupt handler based on the fast interrupt request, wherein the second priority level 3 Appeal 2016-006494 Application 13/649,762 interrupt invokes a kernel service [,]” within the meaning of independent claim 1? 1 (Emphasis added). Regarding the claimed “fast interrupt handler,” we turn to Appellants’ Specification for context, and find a non-limiting description of the following exemplary embodiment: “The ARM processor may be used as an exemplary processor architecture, specifically the ARM fast interrupt request (‘FIQ’) mode, and the software interrupt (‘SWI’) instruction.” (Spec. 4,19,11. 4-6). In reviewing the Examiner’s mapping of the claimed “fast interrupt handler” (Final Act. 7—9) to the corresponding feature found in Warmcat (1), we find a literal description of a “FIQ, or Fast Interrupt Request. This is basically the NMI [(Non Maskable Interrupt)] of the ARM world.” Given this evidence {id.), we find Warmcat teaches or suggests a “fast interrupt handler” within the meaning of contested limitation L, under a broad but reasonable interpretation. Regarding the limitation of “wherein the second priority level interrupt invokes a kernel service” (claim 1, emphasis added), we find the Examiner (Final Act. 9) reads this portion of limitation L on Moore’s “LSR” (Link Service Routine) that is invoked by ISRs [(Interrupt Service Routines)] to do deferred interrupt processing. (Moore, 3). We note Moore (p. 3) expressly discloses that “LSRs are permitted to call all kernel services, but cannot wait for results.” (Emphasis added). Thus, we find 1 We give the contested claim limitations the broadest reasonable interpretation consistent with the Specification. See In re Morris, 111 F.3d 1048, 1054 (Fed. Cir. 1997). 4 Appeal 2016-006494 Application 13/649,762 Moore’s LSRs, when combined to modify Warmcat’s “normal” secondary IRQs, teach or suggest the claimed “second priority level interrupt that invokes a kernel service, within the meaning of contested limitation L. (Moore p. 3). Nevertheless, Appellants focus their arguments on Warmcat, and urge “the FIQ handler of Warmcat cannot raise a second priority level interrupt based on the fast interrupt request, wherein the second priority level interrupt invokes a kernel service, as recited in claim 1.” (App. Br. 5). (Emphasis added). The Examiner responds that “Warmcat was not relied upon to disclose this feature. Rather, it was the combination of Warmcat and Moore which was relied upon to disclose this feature.” (Ans. 8) (Emphasis added). We agree with the Examiner {id.), that Appellants are attacking Warmcat in isolation.2 Further, we find Appellants do not substantively address the Examiner specific findings regarding Moore, as to the contested feature.3 Instead, Appellants merely recite the claim language and assert it is not taught by Moore: “Appellants respectfully submit that, similar to Warmcat, Moore fails to teach or suggest, ‘raising the second priority level interrupt by the fast interrupt handler based on the fast interrupt request, 2 See In re Merck & Co., Inc., 800 F.2d 1091, 1097 (Fed. Cir. 1986) (One cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references.). 3 Mere conclusory statements which are unsupported by factual evidence are entitled to little probative value. In re Geisler, 116 F.3d 1465, 1470 (Fed. Cir. 1997); In re De Blauwe, 736 F.2d 699, 705 (Fed. Cir. 1984). 5 Appeal 2016-006494 Application 13/649,762 wherein the second priority level interrupt invokes a kernel service,’ as recited in claim 1.” (App. Br. 6). The Examiner further explains the basis for the rejection: Warmcat discloses a two part interrupt handling procedure whereby FIQ and IRQ interrupts are physically tied together such that when an FIQ/IRQ occurs during a critical kernel section of processor execution, the FIQ ISR runs first during the critical kernel section (since FIQs are non-maskable) and the IRQ ISR runs after the FIQ ISR and the remainder of the interrupted critical kernel section, when IRQs become unmasked (after completion of the critical kernel section). However, Warmcat does not explicitly disclose raising the IRQ by the FIQ ISR. Moore teaches a similar concept to that of Warmcat whereby an interrupt handler is split into two sections. “The first part does the minimum necessary processing to handle the hardware and to schedule the second part. The second part is performed later, when interrupts are enabled, by a call back mechanism in the scheduler.” (page 1 of Moore) Insofar as the IRQ ISR of Warmcat is scheduled through the raising of the IRQ signal, applying the inferred ISR scheduling teaching of Moore to Warmcat would yield the raising of the IRQ signal during the FIQ ISR thereby rendering the instant claims obvious over the prior art. (Ans. 8—9) (Emphasis added). Thus, as found by the Examiner (id.), Moore (p. 1) expressly describes an “Advanced architecture wherein ISRs are split into two parts. The first part does the minimum necessary processing to handle the hardware and to schedule [, i.e., invoke or “raise”] the second part. The second part is performed later, when interrupts are enabled, by a call back mechanism in the scheduler.” (Emphasis added). 6 Appeal 2016-006494 Application 13/649,762 Appellants respond in the Reply Brief (5—6): Appellants respectfully submit the Examiner has not provided any finding to support the notion that Moore teach[es] the raising the priority level interrupt feature. The Examiner's argument focuses on the teaching of the Moore reference, entitled “Deferred Interrupt Processing,” for processing a second part of IRSs at a deferred time. Specifically, the Examiner notes that Moore discusses the invocation of Link Service Routines (“LSRs”) by ISRs to do deferred interrupt processing. (See 04/14/2016 Examiner's Answer, p. 4, line 12 - p. 5, line 3). The Examiner further cites to Moore discussing an interrupt handler being split into two sections. (See Id., p. 9, lines 5-6). However, simply splitting an interrupt handler into two sections is neither equivalent to nor analogous to raising a priority level interrupt by an interrupt handler based on an interrupt request. Furthermore, the Examiner's Answer provides no support to the Examiner's argument that Moore discloses raising such a priority level interrupt. Even in addressing Appellants argument that Moore is silent to such features, the Examiner merely offers the conclusory statement of, “Moore does disclose such a feature.” Without any attributions or citations to the Moore reference, Appellants maintain that, similar to Warmcat, Moore fails to teach or suggest, “raising the second priority level interrupt by the fast interrupt handler based on the fast interrupt request, wherein the second priority level interrupt invokes a kernel service,” as recited in claim 1. (Reply Br. 5—6). In determining the broadest reasonable interpretation for “raising the second priority level interrupt by the fast interrupt handler based on the fast interrupt request” (claim 1, emphasis added), we turn to Appellants’ Specification for context. We find the following description in paragraphs 33-35: In step 220, the method 200 may execute a fast interrupt handler at a first priority level. As noted above, an ARM processor may be used as an exemplary processor 7 Appeal 2016-006494 Application 13/649,762 architecture. This processor architecture may include a first priority level, such as a fast interrupt request mode (i.e., FIQ mode), and a second priority level, such as a regular interrupt request mode (i.e., IRQ mode). The fast interrupt request mode has a higher priority than the regular interrupt request mode. Thus, when a hardware device asserts a fast interrupt, the processor may immediately enter into fast interrupt request mode regardless of the current mode of the processor. (Spec. 133). Thus, from the above description, we conclude the scope of the claimed “second priority level interrupt” at least covers “a second priority level, such as a regular interrupt request mode (i.e., IRQ mode).” {Id., emphasis added). We note Warmcat (2) expressly describes a two-level interrupt approach: a first fast interrupt “FIQ shadowing with IRQ” (i.e., where IRQ is a second “regular” interrupt) as further described on page 3, in which the fast interrupt “FIQ” signal is physically tied to an “IRQ” input. Although the physical hardware interrupt signals attempt to simultaneously trigger both interrupts because the signals are physically (electrically) tied together {id.), the fast interrupt “FIQ” interrupt has the highest priority because it is described by Warmcat (1) as being non maskable: “the NMI of the ARM world.” Therefore, the FIQ fast interrupt cannot be deferred by any interrupt masking. {See Ans. 9). Accordingly, and responsive to the hardware interrupt signal, the fast FIQ interrupt is invoked first, and the regular secondary “IRQ” will be invoked only when the FIQ exits (i.e., returns from interrupt). Thus, we find when Warmcat’s fast FIQ interrupt exits (returns from interrupt), this exit immediately triggers (i.e., “raises”) a second priority “IRQ” interrupt, 8 Appeal 2016-006494 Application 13/649,762 which inspects the contents of a FIFO, in the manner described at Warmcat (3). As previously discussed, Moore (1) describes “an Advanced architecture wherein ISRs [(Interrupt Service Routines)] are split into two parts” in which “LSR” interrupts (the second part) are presented as “an efficient mechanism for deferring interrupt processing” (2,11. 2—3). Further, Moore (3) expressly teaches that “LSRs are permitted to call all kernel services . . . .” (Emphasis added). Turning again to Appellants’ Specification, paragraph 34 describes: “In step 230, the method 200 may raise a second priority level interrupt based on the fast interrupt request using the fast interrupt handler to invoke a kernel service.” (Emphasis added). As recited in contested limitation L, “the second priority level interrupt invokes a kernel service . . . .” (Claim 1). We note the Specification (| 35) describes an exemplary, non-limiting approach to raising an interrupt: According to the exemplary embodiments described herein, the “swi” instruction is a mechanism to allow software to raise a normal priority interrupt (i.e., IRQ mode). Accordingly, this instruction may be used on ARM processors as a potential method to allow a FIQ handler to post kernel work to be performed at normal priority interrupt level. For example, the FIQ handler could invoke the fiqSemGive) primitive, and the fiqSemGive() primitive would then issue a “swi” instruction, along with providing some basic information in a data queue, so that the actual semGive() operation can be performed at the normal interrupt priority. Thus, in Appellants’ Specification (| 35), according to one exemplary embodiment, the FIQ “fast” interrupt handler invokes or raises a second priority level interrupt by simply calling a software interrupt instruction 9 Appeal 2016-006494 Application 13/649,762 (“SWI”). However, we note claim 1 is silent regarding any mention of a “SWI” (software interrupt) instruction. Therefore, on this record, we are not persuaded of error regarding the Examiner’s ultimate legal conclusion of obviousness, which is based on the underlying factual findings that Warmcaf s fast interrupt request (FIQ) is operatively coupled (by a return from interrupt) with the invocation (i.e, calling or “raising”) of a second IRQ interrupt (i.e., an LSR interrupt in Moore that replaces the “normal” IRQ in Warmcat), in which the LSR interrupt is capable of invoking a kernel service. (Moore p. 3). Our reviewing court guides: “the question under 35 U.S.C. § 103 is not merely what the references expressly teach but what they would have suggested to one of ordinary skill in the art at the time the invention was made.” Merck & Co., Inc. v. Biocraft Laboratories, Inc., 874 F. 2d 804, 807—808 (Fed. Cir. 1989). (Citations and quotation marks omitted). This reasoning is applicable here. Nor do Appellants substantively contest the Examiner’s proffered rationale to combine the Warmcat and Moore references. (Final Act. 9—10). Therefore, given the strength of the evidence cited by the Examiner (Final Act. 7—10; Ans. 8—12), we find the cited combination of Warmcat and Moore teaches or at least suggests contested limitation L. We note contested limitation L is recited in identical form in each of independent claims 1, 9, and 14. Moreover, on this record, and based upon a preponderance of the evidence, we are not persuaded the Examiner’s proffered combination of Warmcat and Moore would have been anything more than a “predictable use of prior art elements according to their established functions.” KSR Int 7 Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007). Accordingly, we sustain the 10 Appeal 2016-006494 Application 13/649,762 rejection of representative claim 1. The remaining claims on appeal fall with claim 1. See Grouping of Claims, supra. Conclusion For at least the aforementioned reasons, and on this record, Appellants have not persuaded us the Examiner erred. We find a preponderance of the evidence supports the Examiner’s underlying factual findings and ultimate legal conclusion of obviousness for all contested claims on appeal. DECISION We affirm the Examiner’s decision rejecting claims 1—3 and 5—20 under § 103(a). No time period for taking any subsequent action in connection with this appeal may be extended under 37 C.F.R. § 1.136(a). See 37 C.F.R. § 41.50(f). AFFIRMED 11 Copy with citationCopy as parenthetical citation