Ex Parte Freytag

Board of Patent Appeals and Interferences

Jan 6, 2010

11130536 (B.P.A.I. Jan. 6, 2010)

UNITED STATES PATENT AND TRADEMARK OFFICE
__________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
__________

Ex parte VINCENT R. FREYTAG
__________

Appeal 2009-009590
Application 11/130,536
Technology Center 2100
__________

Decided: January 6, 2010
__________

Before JEAN R. HOMERE, ST. JOHN COURTENAY III, and
STEPHEN C. SIU, Administrative Patent Judges.

SIU, Administrative Patent Judge.

DECISION ON APPEAL
STATEMENT OF THE CASE
This is a decision on appeal under 35 U.S.C. § 134(a) from the
Examiner’s rejection of claims 1-20. We have jurisdiction under 35 U.S.C.
§ 6(b).
We affirm-in-part.
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Invention
The invention relates to a bus interface adapted to coalesce snoop
responses received from processor cores into a single snoop response that
reflects all of the snoop responses received (Spec. 2).
Independent claim 13 is illustrative:
13. A method for handling snoop responses in a processor
comprising:
monitoring snoop responses directly from at least two
processor cores for passage to a bus;
receiving snoop responses from the at least two processor
cores;
coalescing the snoop responses into a single snoop
signoff that reflects the snoop responses from the at least
two processor cores; and
passing the single snoop signoff to the bus.
References
The Examiner relies upon the following references as evidence in
support of the rejections:
Arimilli1 US 6,279,086 B1 Aug. 21, 2001
Fu US 6,292,906 B1 Sep. 18, 2001
Chin US 6,356,972 B1 Mar. 12, 2002
Moran US 6,738,869 B1 May 18, 2004

1 The Examiner also lists Arimilli, US 6,615,322 B2 (Sep. 2, 2003) (Ans. 2).
However, the Examiner does not rely on the ’322 patent (Fin. Rej.; Ans.).
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Rejections
Claim 13 is rejected under 35 U.S.C. § 102(b) as being anticipated by
Arimilli.
Claims 1-3, 7-9, and 18 are rejected under 35 U.S.C. § 103(a) as being
unpatentable over Arimilli and Moran.
Claims 4, 5, 10, 11, 14-17, 19, and 20 are rejected under 35 U.S.C.
§ 103(a) as being unpatentable over Arimilli, Moran, and Chin.
Claims 6 and 12 are rejected under 35 U.S.C. § 103(a) as being
unpatentable over Arimilli, Moran, Chin, and Fu.
ISSUE 1
Appellant argues that “[t]he combined operation in Arimilli is sent by
a cache or a storage device” (App. Br. 7).
Issue: Did Appellant demonstrate that the Examiner erred in finding
that Arimilli teaches receiving snoop responses from processor cores?
ISSUE 2
Appellant argues that “Arimilli combines internally selected operation
responses to form [a] combined operation” (App. Br. 7). Appellant further
argues that Arimilli’s “[combined] operation responses are not related to
snoop signoffs” (id.).
Issue: Did Appellant demonstrate that the Examiner erred in finding
that Arimilli teaches coalescing snoop responses into a single snoop signoff?
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ISSUE 3
Appellant argues that Arimilli “passes all snoop responses directly to
the bus” (Reply Br. 3).
Issue: Did Appellant demonstrate that the Examiner erred in finding
that Arimilli teaches passing a single snoop signoff to a bus?
ISSUE 4
Appellant argues that Arimilli “discusses storing coherency states
Modified, Exclusive, Shared, and Invalid, which are not related to snoop
responses, such as hit, and hit modified” (App. Br. 9). Moran discuses
“storing a validity bit, but as in Arimilli, what is being stored is a coherency
state, not a snoop response” (id.).
Issue: Did Appellant demonstrate that the Examiner erred in finding
that Arimilli and Moran teach or suggest an array of multiple-bit elements,
each element comprising a hit response bit, a hit modified response bit, and a
valid bit?
ISSUE 5
Appellant argues that “Arimilli, Moran, and Chin . . . do not teach or
suggest anything about hit snoop responses or hit modified snoop responses
from processor cores” (App. Br. 10). “[C]oherency states Modified,
Exclusive, Shared, and Invalid . . . are not related to snoop responses, such
as hit, and hit modified” (id.). Appellant further argues that “detecting
multiple conditions (for example, hit response from one core, no hit
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modified responses from any processor cores) . . . are not taught or
suggested by Arimilli, Moran, and Chin” (id.).
Issue: Did Appellant demonstrate that the Examiner erred in finding
that Arimilli, Moran, and Chin teach or suggest detecting multiple
conditions based on hit and hit modified snoop responses from processor
cores?
FINDINGS OF FACT
The following Findings of Fact (FF) are shown by a preponderance of
the evidence.
1. Appellant’s depiction of processor cores 106 is opaque;
individual caches and processing mechanisms are not shown
(Spec. fig. 1A).
2. Appellant admits in the Specification’s background
section that “[p]rocessors in multi-processor systems include
hierarchical inclusive caches in which higher level caches store
the same cache lines stored in lower level caches” (Spec. 1,
¶ [0002]).
3. Appellant discloses that “a single snoop [signoff] . . .
reflects the snoop responses from the [one or more] processor
cores 206” (Spec. 8, ¶ [0024]).
4. Arimilli teaches that
[e]ach processor 102aa-102mn includes a respective
level one (L1) cache 104aa-104mn, preferably on chip
with the processor and bifurcated into separate
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instruction and data caches. Each processor 102aa-
102mn is coupled via a processor bus 106aa-106l to a
level two [L2] cache 108a-108l.
(Col. 4, ll. 14-18).
5. Arimilli teaches that “[s]noop logic 404, 406 and 408
[snoopers] . . . drive[] merged response[s] with any appended
information to the combined response logic 410” (col. 8,
ll. 61-63).
6. Arimilli teaches that the snoopers are part of level two
(L2) caches (fig. 4A).
7. Arimilli teaches that
[c]ombined response logic 410 receives the merged
responses of snoop logic 404, 406 and 408 and generates
a combined response to be driven on system bus 112.
Appended to the combined response is the coherency
state and LRU [least-recently-used] position of the victim
within each snooper.
(Col. 8, l. 64 to col. 9, l. 1).
8. Arimilli teaches that “the basic MESI coherency protocol
. . . includes the modified (M), exclusive (E), shared (S), and
invalid (I) coherency states” (col. 6, ll. 7-9).
9. Arimilli teaches that
[b]ased on the presence or absence of the subject cache
line within a corresponding storage device and the
coherency state of the subject cache line, snoop logic
404, 406 and 408 selects appropriate responses to the
data access and cast out/deallocate operations. . . .
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. . . Snoop logic 404, 406 and 408 also appends the
cache state for the cast out/deallocate victim—i.e., the
coherency state, the LRU position, or both—to the
merged response.
(Col. 8, ll. 42-56).
10. Moran teaches “a flag indicative of the continued validity
of . . . ownership of [a] resource” (col. 5, ll. 46-48).
PRINCIPLES OF LAW
Claim interpretation
“In the patentability context, claims are to be given their broadest
reasonable interpretations. . . . [L]imitations are not to be read into the
claims from the specification.” In re Van Geuns, 988 F.2d 1181, 1184 (Fed.
Cir. 1993) (citations omitted). A claim meaning is reasonable if one of
ordinary skill in the art would understand the claim, read in light of the
specification, to encompass the meaning. See In re American Academy of
Science Tech Center, 367 F.3d 1359, 1364 (Fed. Cir. 2004). Any special
meaning assigned to a term “must be sufficiently clear in the specification
that any departure from common usage would be so understood by a person
of experience in the field of the invention.” Multiform Desiccants Inc. v.
Medzam Ltd., 133 F.3d 1473, 1477 (Fed. Cir. 1998).
Anticipation
In rejecting claims under 35 U.S.C. § 102, “[a] single prior art
reference that discloses, either expressly or inherently, each limitation of a
claim invalidates that claim by anticipation.” Perricone v. Medicis Pharm.
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Corp., 432 F.3d 1368, 1375 (Fed. Cir. 2005) (citation omitted). “[I]f
granting patent protection on the disputed claim would allow the patentee to
exclude the public from practicing the prior art, then that claim is
anticipated, regardless of whether it also covers subject matter not in the
prior art.” Atlas Powder Co. v. IRECO, Inc., 190 F.3d 1342, 1346 (Fed Cir.
1999) (internal citations omitted).
Obviousness
The question of obviousness is resolved on the basis of underlying
factual determinations including (1) the scope and content of the prior art,
(2) any differences between the claimed subject matter and the prior art, and
(3) the level of skill in the art. Graham v. John Deere Co., 383 U.S. 1, 17-
18 (1966).
New Arguments
“[I]t is inappropriate for appellants to discuss in their reply brief
matters not raised in . . . the principal brief[]. Reply briefs are to be used to
reply to matter[s] raised in the brief of the appellee.” Kaufman Company v.
Lantech, Inc., 807 F.2d 970, 973 n.* (Fed. Cir. 1986). “Considering an
argument advanced for the first time in a reply brief . . . is not only unfair to
an appellee but also entails the risk of an improvident or ill-advised opinion
on the legal issues tendered.” McBride v. Merrell Dow and Pharms., Inc.,
800 F.2d 1208, 1211 (D.C. Cir. 1986) (internal citations omitted).
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ANALYSIS
Issue 1
Based on Appellant’s arguments in the Appeal Brief, we will decide
the appeal with respect to issue 1 on the basis of claim 13 alone. See 37
C.F.R. § 41.37(c)(1)(vii).
Appellant “retracts the statement that Arimilli does not teach or
suggest receiving snoop responses” (Reply Br. 2). However, Appellant “still
asserts that Arimilli does not receive snoop responses directly from cores”
(id.).
The Examiner finds that a “processor core” can be reasonably
interpreted to be Arimilli’s processors and level two caches combined
(Ans. 14; FF 4). Appellant argues that this finding is erroneous because “the
examiner has not cited any . . . evidence that [many processor cores include
L1 and L2 caches directly on the core chip]” (Reply Br. 3). Yet, the claims
are not limited to processor cores with caches directly on a processor chip.
Moreover, Appellant admits that the prior art contains “[p]rocessors in
multi-processor systems [that] include hierarchical inclusive caches” (FF 2).
Hierarchical caches would have multiple levels.
Furthermore, Appellant has not offered any evidence to show that an
artisan would interpret processor core narrowly. Appellant only cites the
opaque core depiction of figure 1A in summarizing the claimed subject
matter (App. Br. 2; FF 1). The processing mechanisms and caches within a
core are not even depicted (FF 1). Thus, we find no error in the Examiner’s
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construction of “processor cores” as inclusive of the combination of the
processors and L2 caches of Arimilli.
Arimilli teaches that snoopers drive merged responses (FF 5). These
snoopers are part of L2 caches (FF 6). Each L2 cache is part of a processor
core. Accordingly, Arimilli teaches receiving snoop responses (merged
responses) from processor cores (snoopers on L2 caches).
Appellant argues that claim 13 in particular “specifies monitoring
snoop responses directly from at least two processor cores” (Reply Br. 2).
This argument is untimely and therefore waived. Moreover, it is
unpersuasive. Appellant has provided no evidence that an artisan of
ordinary skill would understand “monitoring directly” as precluding use of a
bus. In summarizing the claims, Appellant fails to even identify where to
find a “monitoring directly” teaching (App. Br. 4).
For at least these reasons, we find that Appellant has not sustained the
requisite burden on appeal in providing arguments or evidence persuasive of
error in the Examiner’s 35 U.S.C. § 102(b) rejection of claim 13 or in the
Examiner’s 35 U.S.C. § 103(a) rejection of claims 1-12 and 14-20 with
respect to this issue.
Issue 2
Based on Appellant’s arguments in the Appeal Brief, we will decide
the appeal with respect to issue 2 on the basis of claim 13 alone. See 37
C.F.R. § 41.37(c)(1)(vii).
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A single snoop signoff reflects the snoop responses from one or more
process cores (FF 3). Arimilli teaches that a combined response logic
receives merged responses from snoopers (FF 7). The combined response
logic then generates a combined response with the coherency state and LRU
information from each snooper (id.). This combined response reflects (i.e.,
has information derived from) the merged responses. Therefore, Arimilli
teaches coalescing (generating) snoop responses (merged responses) into a
single snoop signoff (combined response).
For at least these reasons, we find that Appellant has not sustained the
requisite burden on appeal in providing arguments or evidence persuasive of
error in the Examiner’s 35 U.S.C. § 102(b) rejection of claim 13 or in the
Examiner’s 35 U.S.C. § 103(a) rejection of claims 1-12 and 14-20 with
respect to this issue.
Issue 3
Based on Appellant’s arguments in the Appeal Brief, we will decide
the appeal with respect to issue 3 on the basis of claim 13 alone. See 37
C.F.R. § 41.37(c)(1)(vii).
Appellant argues that claim 13 in particular “specifies coalescing
snoop responses into a single snoop signoff and passing the single snoop
response to the bus” (Reply Br. 3). This argument is untimely and
unpersuasive. Nothing in the claims precludes other information, such as the
original snoop responses, from going over the bus. Moreover, the combined
response of Arimilli is driven on the bus (FF 7). This accords with
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Appellant’s admission that in Arimilli “every snoop response is appended to
[a] combined operation . . . which is then passed to the bus” (Reply Br. 3).
Therefore, Arimilli teaches passing a single snoop signoff (combined
response) to a bus.
For at least these reasons, we find that Appellant has not sustained the
requisite burden on appeal in providing arguments or evidence persuasive of
error in the Examiner’s 35 U.S.C. § 102(b) rejection of claim 13 or in the
Examiner’s 35 U.S.C. § 103(a) rejection of claims 1-12 and 14-20 with
respect to this issue.
Issue 4
Arimilli teaches the MESI protocol modified, exclusive, shared, and
invalid coherency states (FF 8). Arimilli also teaches that the merged
responses submitted by snoopers are based on the presence or absence of the
subject cache line within the corresponding storage device (FF 9). These
merged responses include the coherency state for the cast out/deallocate
victim (id.). Thus, merged responses reflect whether the cache line was
found along with the coherency state of the cache line. Therefore, a merged
response with the coherency state exclusive corresponds to a hit snoop
response; a merged response with the coherency state modified corresponds
to a hit modified snoop response.
It is insufficient that Arimilli teaches these snoop responses. “Claims
3 and 9 specify storage of bit fields for each processor core, the bit fields
comprising a hit response bit, a hit modified response bit, and a valid bit”
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(App. Br. 8). The Examiner relies on the exclusive and modified states to
teach the hit response and hit modified response bits (Ans. 6). However, the
existence of two different snoop response states, combined with a validity
bit, does not necessarily teach or suggest the three claimed bits.
Appellant claims both a hit response bit and a hit modified response
bit (claims 3, 9). This means that the hit response and hit modified response
indications are independent from each other (i.e., either response, neither
response, or both responses can be stored). The Examiner has not identified
any teachings or suggestions in Arimilli to show that the modified and
exclusive coherency indications are independent from each other. Arimilli
teaches that a merged response can show the hit (exclusive) or hit modified
(modified) states. A merged response can show neither state (e.g., invalid).
But the Examiner has not shown that a merged response can indicate both hit
and hit modified responses simultaneously. Therefore, Arimilli’s teachings
of exclusive and modified states fall short of teaching or suggesting hit
response and hit modified response bits.
Furthermore, the Examiner has not shown that Moran cures this
deficiency. Moran teaches a validity flag (FF 10). But the Examiner has not
shown that combining a validity flag with Arimilli teaches or suggests hit
response and hit modified response bits.
For at least these reasons, we find that Appellant has sustained the
requisite burden on appeal in providing arguments or evidence persuasive of
error in the Examiner’s 35 U.S.C. § 103(a) rejection of claims 3 and 9 with
respect to this issue.
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Issue 5
Based on Appellant’s arguments in the Appeal Brief, we will decide
the appeal with respect to issue 5 on the basis of claim 5 alone. See 37
C.F.R. § 41.37(c)(1)(vii).
As discussed for issue 4, Arimilli teaches hit and hit modified snoop
responses (FF 8, 9). These teachings are insufficient to sustain the
Examiner’s rejection of claims 3 and 9, which require hit and hit modified
response bits. Claim 5, however, does not recite these limitations. Instead,
it addresses logic that reacts to hit responses and hit modified responses. An
artisan of ordinary skill would not understand hit responses and hit modified
responses as necessitating hit and hit modified response bits. Therefore, our
rationale in support of Appellant’s arguments for claims 3 and 9 does not
apply to claim 5.
Appellant argues that the Examiner’s “cites do not support the
examiner’s assertion that Arimilli teaches the claimed conditions” (App.
Br. 10). This argument provides insufficient rationale or evidence to show
error. “A statement which merely points out what a claim recites will not be
considered an argument for separate patentability of the claim.” 37
C.F.R. § 41.37(c)(1)(vii) (2008).
Furthermore, Arimilli teaches that the combined response logic
receives merged responses from snoopers (FF 7). The combined response
logic then generates a combined response with coherency state and LRU
information appended from each snooper (id.). Thus, Arimilli teaches logic
that forms a hit response when a merged response indicates a hit response
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and no hit modified responses are received (i.e., the appended coherency
states reflects the hit response with no hit modified responses). Similarly,
Arimilli teaches logic that forms a hit modified response when a merged
response indicates a hit modified response (i.e., the appended coherency
states reflect that a hit modified response was received). Therefore, Arimilli
teaches detection of multiple conditions (coherency state combinations)
based on hit and hit modified merged responses from processor cores
(snoopers).
For at least these reasons, we find that Appellant has not sustained the
requisite burden on appeal in providing arguments or evidence persuasive of
error in the Examiner’s 35 U.S.C. § 103(a) rejection of claims 5, 11, 16, 17,
and 20 with respect to this issue.
CONCLUSIONS OF LAW
Based on the findings of facts and analysis above, we conclude that
Appellant has not demonstrated:
1. that the Examiner erred in finding that Arimilli teaches receiving
snoop responses from processor cores (issue 1);
2. that the Examiner erred in finding that Arimilli teaches coalescing
snoop responses into a single snoop signoff (issue 2);
3. that the Examiner erred in finding that Arimilli teaches passing a
single snoop signoff to a bus (issue 3); and
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4. that the Examiner erred in finding that Arimilli, Moran, and Chin
teach or suggest detecting multiple conditions based on hit and hit modified
snoop responses from processor cores (issue 5).
However, Appellant has demonstrated that the Examiner erred in
finding that Arimilli and Moran teach or suggest an array of multiple-bit
elements, each element comprising a hit response bit, a hit modified
response bit, and a valid bit (issue 4).
DECISION
We affirm the Examiner’s decision rejecting claim 13 under 35 U.S.C.
§ 102 and rejecting claims 1, 2, 4-8, 10-12, and 14-20 under 35 U.S.C.
§ 103(a).
We reverse the Examiner’s decision rejecting claims 3 and 9 under 35
U.S.C. § 103(a).
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

AFFIRMED-IN-PART

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