Ex Parte Frank et al

Patent Trial and Appeal Board

Oct 3, 2013

11739322 (P.T.A.B. Oct. 3, 2013)

UNITED STATES PATENT AND TRADEMARK OFFICE
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BEFORE THE PATENT TRIAL AND APPEAL BOARD
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Ex parte MICHAEL FRANK,
SANTIAGO FERNANDEZ-GOMEZ,
ROBERT W. LAKER, and AKI NIIMURA
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Appeal 2011-005104
Application 11/739,322
Technology Center 2100
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Before ROBERT E. NAPPI, IRVIN E. BRANCH, and PETER P. CHEN,
Administrative Patent Judges.

NAPPI, Administrative Patent Judge.

DECISION ON APPEAL
Appeal 2011-005104
Application 11/739,322

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This is a decision on appeal under 35 U.S.C. § 6(b) of the rejection of
claims 28 through 47.
We affirm in part.

INVENTION
The invention is directed to a method for reducing the response time
for requests for information stored in memory. See paragraphs 0005 through
0007 of Appellants’ Specification. Claim 28 is reproduced below:
28. A method comprising:
concurrently providing a first request to access first data
from a bus controller to a bus interface unit to access the first
data from a cache and to a memory controller to access the first
data from a memory; and
terminating processing of the first request at the memory
controller responsive to the bus interface unit responding with
data from the cache for the first request prior to the memory
controller responding with data from the memory for the first
request.

REJECTION AT ISSUE
The Examiner has rejected claims 28 through 47 under 35 U.S.C.
§ 102(b) as anticipated by Kumar (U.S. 6,237,064 B1, May 22, 2001).
Answer 4-5.1

1 Throughout the opinion we refer to the Appellants’ Brief dated September
8, 2010 (“Brief”), Reply Brief dated January 19, 2011, and the Examiner’s
Answer mailed November 19, 2010.
Appeal 2011-005104
Application 11/739,322

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ISSUES
Appellants argue on pages 4 through 7 and 9 of the Brief, and pages 2
and 3 of the Reply Brief that the Examiner’s anticipation rejection is in
error. Appellants’ arguments present us with the following issues:
a) With respect to independent claims 28 and 40, did the
Examiner err in finding that Kumar describes terminating a request for
data access at a memory controller as recited in representative claim
28?
b) With respect to independent claim 36, did the Examiner
err in finding that Kumar describes delaying providing data from the
memory controller until the response from the bus interface unit is
received?

ANALYSIS
We have reviewed the Examiner’s rejections in light of Appellants’
contentions that the Examiner has erred. Further, we have reviewed the
Examiner’s response to Appellants’ arguments. We disagree with
Appellants’ conclusion that the Examiner erred in finding that Kumar
describes terminating a request for data access at a memory controller.
However, we agree with Appellants that Kumar fails to describe delaying
providing data from the memory controller until the response from the bus
interface unit is received.

Claims 28 through 35 and 40 through 47
Appellants argue that Kumar does not teach that memory controller
110 terminates the request as claimed. Brief 5. Further, Appellants argue
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Application 11/739,322

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the Examiner’s interpretation of a memory controller including the queue
and its control logic is unreasonable. Specifically, Appellants argue the FSB
queue tracks memory requests submitted to memory and that “the mere
tracking of memory requests/transactions not the same as controlling access
to a memory, or even accessing a memory.” Brief 6, 7 (emphasis omitted).
The Examiner responds to Appellants’ arguments stating that the term
“memory controller” has been given the broadest reasonable interpretation
and as such, finds that the FSB queue and memory controller (item 110) of
Kumar meet the claimed memory controller. Answer 8-9. We concur with
the Examiner’s claim interpretation. Appellants’ arguments have not cited a
definition that precludes the Examiner’s interpretation of the controller
including a queue. Further, we note that Appellants’ assertion that tracking
memory requests is not part of memory controller appears to be at odds with
Appellants’ Specification. Specifically, paragraph 41 of Appellants’
Specification discusses the memory controller making use of a queue to
track memory requests. Accordingly, Appellants’ arguments have not
persuaded us that the Examiner erred in finding that Kumar describes
terminating a request for data access at a memory controller. Thus, we
sustain the Examiner’s rejection of representative claim 28, and claims 29
through 35 and 40 through 47 which are grouped with claim 28.

Claims 36 through 39
Appellants argue Kumar does not teach delaying processing data from
memory. Brief 8. The Examiner finds that Kumar’s teaching of
concurrently requesting data from two levels of memory and ignoring
information found meets the claimed delay. Answer 11-12 (citing col. 4,
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ll. 14-21). In response to the Examiner’s finding the Appellants argue that
Kumar does not disclose that the ignored response is delayed relative to a
response from a bus interface unit. Reply Brief 4. We concur with
Appellants. We disagree with the Examiner’s finding that Kumar column 4
discloses the ignoring of information retrieved in a manner that meets the
claimed delay. Thus, we are persuaded of error in the Examiner’s rejection
of independent claim 36 and dependent claims 37 through 39.

DECISION
We sustain the Examiner’s rejections of claims 28 through 35 and 40
through 47.
We do not sustain the Examiner’s rejection of claim 36 through 39.
The decision of the Examiner to reject claims 28 through 47 is
affirmed-in-part.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

AFFIRMED-IN-PART

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