Ex Parte FernaldDownload PDFPatent Trial and Appeal BoardDec 15, 201613563683 (P.T.A.B. Dec. 15, 2016) Copy Citation United States Patent and Trademark Office UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O.Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 13/563,683 07/31/2012 Kenneth W. Fernald 5797-05700 9482 35690 7590 12/19/2016 MEYERTONS, HOOD, KIVLIN, KOWERT & GOETZEL, P.C. P.O. BOX 398 AUSTIN, TX 78767-0398 EXAMINER NAM, HYUN ART UNIT PAPER NUMBER 2184 NOTIFICATION DATE DELIVERY MODE 12/19/2016 ELECTRONIC Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the following e-mail address(es): patent_docketing@intprop.com ptomhkkg @ gmail .com PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE BEFORE THE PATENT TRIAL AND APPEAL BOARD Ex parte KENNETH W. FERNALD Appeal 2015-007893 Application 13/563,683 Technology Center 2100 Before ALLEN R. MacDONALD, DANIEL J. GALLIGAN, and DAVID J. CUTITTAII, Administrative Patent Judges. MacDONALD, Administrative Patent Judge. DECISION ON APPEAL Appeal 2015-007893 Application 13/563,683 STATEMENT OF CASE Appellant appeals under 35 U.S.C. § 134(a) from a rejection of claims 1—20. We have jurisdiction under 35 U.S.C. § 6(b). Exemplary Claim Exemplary claim 1 under appeal read as follows (emphasis and bracketing added): 1. An apparatus, comprising: [(A)] a direct memory access (DMA) controller coupled to a bus; [(B)] a data transfer management (DTM) circuit; [(C)] a processor configured to execute program instructions to configure the DTM circuit to provide DMA requests to the DMA controller, wherein the DMA requests cause the DMA controller to perform: [(i)] retrieving a data object; and [(ii)] transmitting the data object to a peripheral circuit via the bus. Rejection on Appeal The Examiner rejected claims 1—20 under 35 U.S.C. § 102(b) as being anticipated by Knight et al. (US 2004/0030816 Al; Feb. 12, 2004).1 1 Separate patentability is argued for claims 1, 5, 7, and 12. Claims 1—4, 6, 8—11, 13—16, and 18 are grouped with claim 1. Claim 17 is grouped with claim 5. Claims 19 and 20 are grouped with claim 12. Except for our ultimate decision, the rejections of claims 2—4, 6, 8—11, and 13—20 are not discussed further herein. 2 Appeal 2015-007893 Application 13/563,683 Appellant’s Contentions2 1. Appellant contends that the Examiner erred in rejecting claim 1 under 35 U.S.C. § 102(b) because: Knight does not teach NextPort Logic 120 “provid[ing] DMA requests to [a] DMA controller,” as recited in claim 1. App. Br. 7, emphasis omitted. Knight discloses “NextPort logic 120 [being able to] call [an] appropriate handler routine for the chosen transmission or reception port.” Knight at 1 [0039]. Knight, however, discloses “executing the selected handler routine at the processor to process a data transfer with the selected I/O device or DMA controller,” (emphasis added) id. at 1 [0009]. See also id. at I [0042] (describing “loading] the handler routine address into the processor's program counter” in initiating execution). Thus, even assuming arguendo that the calling of this routine constitutes providing a DMA request, Knight’s NextPort Logic 120 would be providing this request to processor 112, not one of DMA controllers 136 or 138. Again, Knight’s processor is still responsible for “perform [ing\ DMA operations on [] devices. ” Id. at 1 [0045]. Knight’s NextPort Logic 120 is merely aggregating information from I/O devices 130 and controllers 138 in order to recommend the next port for processor 112 to service (as implied by the name “NextPort Logic”). See id. at II [0036]-[0038]. Appellant therefore submits that Knight’s NextPort Logic 120 cannot constitute the recited “DTM circuit” of claim 1 as NextPort Logic does not “provide DMA requests to [a] DMA controller, ” as recited in claim 1. App. Br. 7—8, emphasis in bold and italics added. 2 These contentions are determinative as to the rejections on appeal. Therefore, Appellant’s other contentions are not discussed herein. 3 Appeal 2015-007893 Application 13/563,683 2. Appellant contends that the Examiner erred in rejecting claim 5 under 35 U.S.C. § 102(b) because: Appellant respectfully submits that it is unclear why Fig. 2 is cited by the Office Action for the recited “acknowledgement” of claim 5. At best, this figure is merely indicating how execution of a handler routine is invoked. Accordingly, to the extent the table in Fig. 2 is described, Knight does not teach “an acknowledgement corresponding to [a] request [to a DMA controller],” much less teach that NextPort Fogic 120 (the alleged DTM circuit) “provide[s] the acknowledgement [from the DMA controller] to [] two peripheral devices,” as recited in claim 5. App. Br. 9. 3. Appellant contends that the Examiner erred in rejecting claim 7 under 35 U.S.C. § 102(b) because: The Office Action cites to paragraph [0120] in asserting the Knight teaches the recited “reduced power mode” of claim 7. Office Action at 5. Appellant submits that this paragraph does not support the Examiner’s assertion. In paragraph [0120], Knights [sic] presents the accompanying description for Fig. 15, which “illustrates a SDRAM block diagram." At the end of the paragraph, Knight indicates that “[a]nother feature [of the SDRAM] includes a power down mode where a low power mode drastically reduces the power consumed by external SDRAM devices.” As is apparent, Knight is describing operation of an SDRAM device, not a “processor ... entering] a reduced power mode,” as recited in claim 7. App. Br. 10. 4. Appellant contends that the Examiner erred in rejecting claim 12 under 35 U.S.C. § 102(b) because: Knight discloses that an “aspect of [its] invention” pertains to “handling transmission of network packetsM which are 4 Appeal 2015-007893 Application 13/563,683 assembled from multiple memory buffers with different octet alignments” (emphasis). See Knight at | [0008]. Appellant submits, however, that Knight does not discuss “disassembly” of any data packet. Indeed, Knight does not include the words disassemble, disassembling, or disassembly. It therefore follows that Knight does not teach a “DTM circuit [] configured to coordinate disassembly of a received data packet, by generating DMA requests for the DMA controller,” as recited in claim 12. App. Br. 11. Issues on Appeal Did the Examiner err in rejecting claims 1, 5, 7, and 12 as being anticipated? ANALYSIS We have reviewed the Examiner’s rejections in light of Appellant’s arguments that the Examiner has erred. As to Appellant’s above contention 1, the Examiner responds by construing the “a processor configured to execute program instructions to configure the DTM circuit to provide DMA requests to the DMA controller,” limitation of claim 1 as “a processor (configured to executed program instructions to configure the DTM circuit) to provide DMA request to the DMA controller.” Ans. 3. The Examiner then finds “the DMA request indeed originally comes from the processor.” Ans. 3. Appellant responds by asserting “the Examiner’s construction goes beyond what would fall under the broadest reasonable interpretation (BRI) standard and flies against the plain language of the claim’s limitation.” Reply Br. 4. 5 Appeal 2015-007893 Application 13/563,683 We agree with Appellant. We construe the “a processor configured to execute program instructions to configure the DTM circuit to provide DMA requests to the DMA controller,” limitation of claim 1 as —a processor configured to execute program instructions to configure the DTM circuit to cause the DTM circuit to provide DMA requests to the DMA controller— We conclude, consistent with Appellant’s argument, that Knight is insufficient to support the Examiner’s findings. Therefore, we conclude that the record is insufficient to support the Examiner’s determination that claim 1 was anticipated by Knight. As to Appellant’s above contentions 2-4, we agree with the Appellant’s arguments. CONCLUSIONS (1) Appellant has established that the Examiner erred in rejecting claims 1—20 as being anticipated under 35 U.S.C. § 102(b). (2) Claims 1—20 have not been shown to be unpatentable. DECISION The Examiner’s rejection of claims 1—20 is reversed. REVERSED3 3 Should there be further consideration of the application on appeal, the Examiner’s attention is directed to the following: The system of Knight’s Figure 1 “is an illustration of a system for implementing DMA scheduling.” Knight 116. That is the processor 112 of Knight’s Figure 1 is part of the DMA scheduling system, and processor 112 together with NextPort logic 120 form a “data transfer management (DTM) 6 circuit” (as claimed). The Knight reference is directed to the interaction of a DTM circuit (112 & 120) and the DMA controllers (136 & 138). However, Knight is silent as to the overall computer system within which such a DTM circuit would operate. Therefore, Knight is silent as to the “processor” (the central processor unit (CPU) of the overall system) such as in Appellant’s claim 1. In determining obviousness of the subject matter over Knight, we deem the pertinent question to be whether it would have been obvious to an artisan that Knight’s DTM/DMA circuit operates within an overall system having a central processing unit for controlling such circuit. Copy with citationCopy as parenthetical citation