Ex Parte Farrell

Board of Patent Appeals and Interferences

Jul 11, 2011

11218994 (B.P.A.I. Jul. 11, 2011)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
11/218,994 09/01/2005 Todd D. Farrell MISC:0139 (04-0948) 2207
52142 7590 07/11/2011
FLETCHER YODER (MICRON TECHNOLOGY, INC.)
P.O. BOX 692289
HOUSTON, TX 77269-2289
EXAMINER
DINH, NGOC V
ART UNIT PAPER NUMBER
2185
MAIL DATE DELIVERY MODE
07/11/2011 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
____________________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________________

Ex parte TODD D. FARRELL
____________________

Appeal 2009-0105301
Application 11/218,994
Technology Center 2100
____________________

Before JEAN R. HOMERE, ST JOHN COURTENAY III, and
DEBRA K. STEPHENS, Administrative Patent Judges.

HOMERE, Administrative Patent Judge.

DECISION ON APPEAL

1 The real party in interest is Micron Technology, Inc. (App. Br. 2.)
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I. STATEMENT OF THE CASE
Appellant appeals under 35 U.S.C. § 134(a) from the final rejection of
claims 1-3, 5-10, 12-20, and 22-31. Claims 4, 11, and 21 have been
canceled. (App. Br. 2.) We have jurisdiction under 35 U.S.C. § 6(b).
We affirm.
Appellant’s Invention
Appellant invented a buffer controller having a pre-programmed
register that correlates input buffers with different tasks to thereby
dynamically select between a first input buffer type and a second input
buffer type depending on the task a memory device is performing. (Spec. 6,
ll. 1-14.) In particular, upon detecting that the memory device is operating
in a power conservation mode requiring a slower response signal, the buffer
controller (70) therein selects the first type input buffer (68B) having a Low
Voltage Complimentary Metal Oxide Semiconductor (LVCMOS).
Alternatively, the buffer controller (70) selects the second type input buffer
(68A) having a Stub Series Terminated Logic (SSTL) upon detecting that
the memory device is operating in a power consumption mode requiring a
faster response signal. (Fig. 5, Spec. 15, l. 7- Spec. 16, l. 2.)
Illustrative Claim
Independent claim 1 further illustrates the invention. It reads as
follows:
1. A device comprising:
a first type of input buffer adapted to receive a signal;
a second type of input buffer adapted to receive the signal; and
a buffer controller coupled to each of the first and second types
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of input buffers and configured to select dynamically one of the
first type of input buffer and the second type of input buffer
based on a type of task the device is performing, wherein the
buffer controller comprises a mode register pre-programmed to
correlate the first and second types of input buffers with
different types of tasks the device performs.

Prior Art Relied Upon
Lee US 6,943,585 B2 Sept. 13, 2005
Camarota US 7,023,238 B1 Apr. 4, 2006

Rejection on Appeal
The Examiner rejects claims 1-3, 5-10, 12-20, and 22-31 under 35
U.S.C. § 103(a) as being unpatentable over the combination of Lee and
Camarota.
Appellant’s Contentions
Appellant contends that the combination of Lee and Camarota does
teach or suggest a pre-programmed mode register within a buffer controller
that correlates input buffers with different tasks to thereby dynamically
select an input buffer based on the type of task a device is performing, as
recited in independent claim1. In particular, Appellant argues that while Lee
discloses a buffer controller that selects one of a plurality of input buffers,
such selection is performed at runtime, and not in advance as claimed.
(App. Br. 7-8, Reply Br. 2.) Further, Appellant argues that Camarota’s
Programmable Logic Device (PLD) is not pre-programmed, nor does the
selection of different buffers to address varying levels (quiet/noisy) of an
incoming signal cure the noted deficiencies of the Lee reference. (App. Br.
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9-11, Reply Br. 2-5.) Therefore, Appellant submits that the proposed
combination does not render the claimed invention unpatentable. (Id.)

Examiner’s Findings
In response, the Examiner finds that Lee’s disclosure of an input
buffer circuit having a buffer controller that selects between a first CMOS
buffer type requiring lower operation voltage and a second differential
buffer type during normal operation depending on whether an external input
voltage is lower than a reference voltage teaches the claimed dynamic
selection of a buffer type based on a detected mode of operation of the input
buffer device. (Ans. 3, 6-7.) Next, the Examiner finds that Camarota
complements Lee’s teaching by disclosing a PLD having a modified bit that
is configured/pre-programmed to allow a controller transition back and forth
between different buffer types depending on the detected mode of operation
of an input buffer. (Ans. 7.)
Therefore, the pivotal issue before us is as follows:

II. ISSUE
Has Appellant shown that the Examiner erred in finding that the
combination of Lee and Camarota teaches or suggests a pre-programmed
mode register within a buffer controller that correlates input buffers with
different tasks to thereby dynamically select an input buffer based on the
type of task a device is performing, as recited in independent claim 1?

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III. FINDINGS OF FACT
The following Findings of Fact (FF) are shown by a preponderance of
the evidence.
Lee
1. Lee discloses an SSTL interface having a controller (30) for switching
between a CMOS input buffer (20) and a differential input buffer (10)
depending on whether an external voltage received at the input buffer
falls below the reference voltage in differential buffer. In particular,
during normal operation in the power consumption mode (i.e. the
external voltage is greater than the reference voltage), the controller
selects the differential input buffer requiring higher speed. However,
when upon detecting that the external voltage falls below the
reference voltage indicating that the device is operating in a power
conservation mode, the controller selects the CMOS input buffer.
(Fig. 2; col. 2, ll. 47-53, col. 3, ll. 40-50, col. 4, ll. 20-31, col. 8, ll. 1-
18.)

Camarota
2. Camarota discloses an input buffer having an integrated PLD with one
or more switching thresholds depending on the selected mode of
operation of the buffer. In particular, the PLD includes a mode bit
configured to control and select which of the two modes the buffer is
operating in. (Col. 1, ll. 58-65, col. 2, ll. 34-39.)
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3. Camarota further discloses that the integrated PLD may include a
CMOS input buffer and a TTL input buffer, each being selectable for
use. (Col. 5, l. 64- col. 6, l. 12.) In particular, the mode bit is
configured to switch to the first input buffer (LVCMOS) upon
receiving an input signal above a first switching threshold level. The
mode bit is also configured to switch to the second input buffer (TTL)
when the input signal is below a second switching threshold level.
(Col. 8, ll. 1- 42.)

IV. ANALYSIS
We find no error in the Examiner’s rejection of independent claim 1,
which recites, inter alia, a pre-programmed mode register within a buffer
controller that correlates input buffers with different tasks to thereby
dynamically select an input buffer based on the type of task a device is
performing. First, we find that Lee’s controller is programmed to
dynamically select between the CMOS input buffer and the differential input
buffer depending on whether the input buffer is operating in a power
consumption mode or in a power conservation mode. (FF. 1.) In particular,
we find that one of ordinary skill in the art would have readily appreciated
that for the controller to automatically switch from one input buffer to
another depending on the mode of operation, some kind of pre-programming
would be deemed necessary. Further, we find that such programming would
have to entail assigning in advance a particular input buffer to a
corresponding mode of operation (i.e. [power consumption mode –
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differential input buffer] and [power conservation mode-CMOS input
buffer]) for this switching to take place without user intervention at runtime.
Additionally, we find Camarota complements Lee’s teaching by
disclosing configuring a mode bit to permit a controller to switch between an
LVCMOS input buffer and a TTL input buffer depending on whether the
input buffer is operating in a power consumption mode or in a power
conservation mode. (FF. 2-3.) In our view, the ordinarily skill artisan would
have readily recognized that a certain degree of pre-programming would be
required in order to configure the mode bit, which would then have to be
stored in a register for subsequent use by the input buffer. Consequently, we
are satisfied that the combination of Lee and Camarota discloses prior art
elements that perform their ordinary functions to predictably result in an
input buffer having a mode bit stored in a register configured to permit a
controller to automatically and dynamically switch between a LVCMOS
input buffer and a TTL input buffer based on whether the input buffer is
operating in a power consumption mode or power conservation mode. It
follows that Appellant has not shown2 the Examiner erred in finding that the

2 See In re Jung, 637 F.3d 1356, 1365 (Fed. Cir. 2011) (“Jung argues that the
Board gave improper deference to the examiner’s rejection by requiring
Jung to ‘identif[y] a reversible error’ by the examiner, which improperly
shifted the burden of proving patentability onto Jung. Decision at 11. This
is a hollow argument, because, as discussed above, the examiner established
a prima facie case of anticipation and the burden was properly shifted to
Jung to rebut it. . . . ‘[R]eversible error’ means that the applicant must
identify to the Board what the examiner did wrong . . . .”).

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combination of Lee and Camarota teaches or suggests the disputed
limitations.
Since Appellant argues claims 1-3, 5-10, 12-20, and 22-31 as a single
group, claims 2, 3, 5-10, 12-20, and 22-31 fall together with claim 1 for the
same reasons set forth above. See 37 C.F.R. § 41.37(c)(1)(vii).

V. DECISION
We affirm the Examiner’s rejection of claims 1-3, 5-10, 12-20, and
22-31 as set forth above.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

AFFIRMED

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