Ex Parte Farkas et al

Patent Trial and Appeal Board

Apr 28, 2016

12131196 (P.T.A.B. Apr. 28, 2016)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR
12/131, 196 06/02/2008 Sandor T. Farkas
33438 7590 05/02/2016
TERRILE, CANNATTI, CHAMBERS & HOLLAND, LLP
P.O. BOX 203518
AUSTIN, TX 78720
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
DC-14205 5368
EXAMINER
GONZALEZ, HIRAM E
ART UNIT PAPER NUMBER
2848
NOTIFICATION DATE DELIVERY MODE
05/02/2016 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address( es):
tmunoz@tcchlaw.com
kchambers@tcchlaw.com
heather@tcchlaw.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Exparte SANDOR T. FARKAS, FERNANDO MESCHINO,
THOMAS EDWIN GARVENS, MICHAEL JON ROBERTS,
SCOTT MICHAEL RAMSEY, and CHARLES L. HALEY1
Appeal2014-007482
Application 12/131, 196
Technology Center 2800
Before ROMULO H. DELMENDO, CHRISTOPHER L. OGDEN, and
MONTE T. SQUIRE, Administrative Patent Judges.
OGDEN, Administrative Patent Judge.
DECISION ON APPEAL
Appellants appeal under 35 U.S.C. § 134(a) from the Examiner's final
decision rejecting claims 7-11, 13-17, and 19 in the above-identified
application. We have jurisdiction pursuant to 35 U.S.C. § 6(b).
We REVERSE.
1 According to Appellants, the real party in interest is Dell Products L.P.
Appeal Br. 1.
Appeal2014-007482
Application 12/131, 196
BACKGROUND
Appellants' invention relates to an optimized two-socket/four-socket
server architecture. Spec. i-f 1. An embodiment of this architecture is shown
in Figure 3, which is reproduced below:
Buffer ......................
Buffer
10
Buffer
Buffer 1=:::=:~~
Buffer
B:uffer
Figure 3 depicts a block diagram that includes two processors 320, see Spec.
i-fi-127, 31, and two link modules 310 containing loopback connection paths
312, see Spec. i-f 25. While processors may be used in sockets corresponding
to link modules 310 for a 4S architecture, in the absence of these processors,
the loopback connections may be configured for an optimized 2S
architecture using only processors 320. See Spec. i-fi-125-31.
Independent claim 7 is representative:
7. An optimized two socket/-four socket (2S/4S)
information handling system comprising
a motherboard, the mother board comprising four
processor sockets, the four processor sockets being
configured in a four socket topology, the four socket
topology comprising two lower sockets and two upper
sockets;
first and second processors coupled to the two lower
sockets; and,
2
Appeal2014-007482
Application 12/131, 196
a first link module coupled to a first of the two upper
sockets, the first link module comprising a loopback
connection path, the loopback connection path
connecting the first of the upper sockets so as to
optimize the four socket topology to operate as a two
socket topology; and,
a second link module coupled to a second of the two
upper sockets, the second link module comprising a
loopback connection path, the loopback connection
path connecting the second of the upper sockets so as
to optimize the four socket topology to operate as a
two socket topology; and wherein
each of the first and second link modules comprises
connections to provide a proper lane assignment for
the first and second processors, the proper lane
assignment allowing the first link module and the
second link module to be passive without performance
reduction due to signal integrity (SI) degradation.
Appeal Br. 8 (emphasis added). Claims 13 and 19 are also independent, and
contain similar limitations including the emphasized language.
The Examiner maintains the following grounds of rejection: claims
7-11, 13-17, and 19 are rejected under 35 U.S.C. § 103(a) as being
unpatentable over U.S. Patent No. 7 ,512, 731 B2 [hereinafter Yang] (issued
Mar. 31, 2009) in view of U.S. Patent No. 7,106,600 B2 [hereinafterKupla]
(published Sept. 12, 2006). Final Action 2---6. 2
DISCUSSION
The Examiner finds that Yang teaches a link module comprising a
"loopback connection path connecting the first of the upper socket so as to
optimize the four socket topology to operate as a two socket topology."
2 In the Answer, the Examiner withdrew a rejection of claims 7 and 13 under
35 U.S.C. § 112, first paragraph. Answer 2.
3
Appeal2014-007482
Application 12/131, 196
Final Action 3 (citing Yang Fig. 8A, 7: 17-22). Figure 8A of Yang is
reproduced below:
l!D
C'()·N .. T.'RO~ 'lr::::·R .. ~ ·r : : .... L,:: ~.>
21
MEMORY
31
MEMORY
22
liiiiiiiiiiii·i-i
0
i
0
i:iiiiiiiiiiiiil
MEMORY
f;f~
31'
32 "'\...·
MEMORY
22'
liiiiiiiiiiiiii~iiiiiiiiiiiiiil
FIG., 8A
42
42
Figure 8A of Yang depicts "a 4-processor computer system with two
memory bridges." Yang 3:31-32. The Examiner finds that Yang teaches
the "loopback connection path limitation" because "the information travels
through the buses in both directions." Answer 2.
The Examiner provides no basis for interpreting a "loopback path
limitation" as being satisfied by two-way communication through a bus.
The Examiner's interpretation is at odds with that offered by Appellants,
which defines "[l]oopback as the routing of electronic signals back to their
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Appeal2014-007482
Application 12/131, 196
source without intentional processing or modification to provide a means for
testing the transmission or transportation infrastructure." Reply Br. 1.
We give claim limitations their "broadest reasonable interpretation
consistent with the specification." In re Translogic Tech. Inc., 504 F.3d
1249, 1256 (Fed. Cir. 2007) (quoting In re Hyatt, 211F.3d1367, 1372 (Fed.
Cir. 2000). As argued by Appellants, Reply Br. 1, the usage of the disputed
term "loopback" in the Specification is consistent with the ordinary meaning
of the term as it would be understood by a person skilled in the relevant art.
The Specification states that "[i]t is known to use loopback cables,
connectors or modules (all generally referred to as loopback slugs) to
provide connectivity for testing purposes." Spec. i-f 6. In one example, the
Specification states that a loopback connection can be implemented by a link
module that "merely includes a set of electrical connections (e.g., copper
traces) connecting pads (e.g., gold plated pads) on a thick printed circuit
board (PCB) dielectric material that is shaped to fit the processor socket."
Spec. i1 8. In this embodiment, the link module is described as "passive."
Id.
Because the term loopback, as used in the Specification and in the
field of art, appears to denote more than simply communication in two
directions, we determine that the broadest reasonable interpretation of the
term loop back, consistent with the Specification, is reflected in Appellants'
proposed definition, and requires electronic signals to be passed without
intentional processing or modification. We also determine that the
Examiner's interpretation of the phrase loop back connection path in
independent claims 7, 13, and 19 is broader than what is warranted by the
Specification.
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Appeal2014-007482
Application 12/131, 196
As a result, the Examiner has not shown that either Yang or Kupla
discloses a loopback connection path, and therefore has not established a
prima facie case that independent claims 7, 13, and 19 would have been
obvious over the combination of Yang and Kupla. The Examiner's
additional findings regarding dependent claims 8-11 and 14-17 do not
address the above deficiency. Therefore, we determine that the Examiner
reversibly erred in rejecting claims 7-11, 13-17, and 19.
DECISION
The Examiner's decision is reversed.
REVERSED
6