Ex Parte Farhan et al

Patent Trial and Appeal Board

Jun 10, 2016

12543911 (P.T.A.B. Jun. 10, 2016)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE
12/543,911 08/19/2009
27683 7590 06/14/2016
HA YNES AND BOONE, LLP
IP Section
2323 Victory A venue
Suite 700
Dallas, TX 75219
FIRST NAMED INVENTOR
Munif M. Parhan
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
16356.1192 (DC-16896) 8308
EXAMINER
SADLER, NATHAN
ART UNIT PAPER NUMBER
2139
NOTIFICATION DATE DELIVERY MODE
06/14/2016 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address( es):
ipdocketing@haynesboone.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte MUNIF M. F ARHAN and MICHAEL S. BANKS
Appeal2014-005416
Application 12/543,911
Technology Center 2100
Before KAL YANK. DESHPANDE, DAVID M. KOHUT, and
JUSTIN T. ARBES, Administrative Patent Judges.
DESHPANDE, Administrative Patent Judge.
DECISION ON APPEAL
Appeal2014-005416
Application 12/543,911
STATEMENT OF CASE1
Appellants seek review under 35 U.S.C. § 134(a) of the Examiner's
Final Rejection of claims 1-20. We have jurisdiction over the appeal
pursuant to 35 U.S.C. § 6(b).
We AFFIRM.
Appellants' invention is directed to the power optimization of solid
state memory devices. Spec. i-fi-f l-2.
An understanding of the invention can be derived from a reading of
exemplary claim 1, which is reproduced below:
1. A method comprising:
operating a solid state memory device, wherein the solid
state memory device includes a data storage array having a
plurality of data channels intersecting a plurality of data rows,
wherein one of each of a plurality of solid state data storage units
is located at one of a plurality of intersections of the plurality of
data channels and the plurality of data rows;
monitoring a frequency of access of the plurality of solid
state data storage units;
moving data from at least one solid state data storage unit
located at a first subset of the plurality of intersections to at least
one solid state data storage unit located at a second subset of the
plurality of intersections in response to determining that the
frequency of the access of the at least one solid state data storage
unit located at the first subset of the plurality of intersections
exceeds a predetermined level, wherein the moving results in the
first subset of the plurality of intersections in the solid state
memory device including solid state data storage units with a
1 Our decision makes reference to Appellants' Reply Brief ("Reply Br.,"
January 17, 2014), and Appellants' Appeal Brief ("App. Br.," filed October
31, 2013), the Examiner's Answer ("Ans.," mailed December 4, 2013), and
Final Office Action ("Final Act.," mailed June 7, 2013).
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Application 12/543,911
frequency of access below the predetermined level and the
second subset of the plurality of intersections in the solid state
memory device including at least one solid state data storage unit
with a frequency of access above the predetermined level; and
powering down at least one of a first subset of the plurality
of data channels and a first subset of the plurality of data rows in
the solid state memory device that provide the first subset of the
plurality of intersections, and providing power to the second
subset of the plurality of intersections.
REFERENCES
The Examiner relies on the following prior art:
Tanaka US 2008/0172523 Al July 17, 2008
(filed Jan. 3, 2008)
Mar. 5, 2009 Cho US 2009/0063791 Al
(filed July 17, 2008)
REJECTION
Claims 1-20 stand rejected under 35 U.S.C. § 103(a) as obvious over
Cho and Tanaka. Final Act. 2---6.
ISSUES
The issue of whether the Examiner erred in rejecting claims 1-20
under 35 U.S.C. § 103(a) as obvious over Cho and Tanaka turns on whether
the combination of Cho and Tanaka teaches:
powering down at least one of a first subset of the plurality
of data channels and a first subset of the plurality of data rows in
the solid state memory device that provide the first subset of the
plurality of intersections, and providing power to the second
subset of the plurality of intersections
as recited in independent claim 1, and similarly recited in independent
claims 8 and 15.
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Application 12/543,911
The issue of whether the Examiner erred in rejecting claims 4, 11, and
18 under 35 U.S.C. § 103(a) as obvious over Cho and Tanaka turns on
whether Tanaka teaches that the "solid state memory device is a solid state
drive and each of the plurality of solid state data storage units is a solid state
chip," as recited in dependent claim 4, and similarly recited in dependent
claims 11 and 18.
ANALYSIS
Claims 1-3, 5-10, 12-17, 19, and 20
Independent claim 1 requires a solid state memory device comprising
a data storage array with data storage units located at a plurality of
intersections of a plurality of data channels and rows. Appellants argue that
the combination of Cho and Tanaka does not teach:
powering down at least one of a first subset of the plurality
of data channels and a first subset of the plurality of data rows in
the solid state memory device that provide the first subset of the
plurality of intersections, and providing power to the second
subset of the plurality of intersections,
as recited in independent claim 1, and similarly recited in claims 8 and 15.
App. Br. 6-10; Reply 4--5. Specifically, Appellants argue that the
combination of Cho and Tanaka fails to teach the disputed limitation
because the combination does not teach powering down at least one of a first
subset of a plurality of data channels and at least one of a first subset of a
plurality of data rows in a solid state memory device. App. Br. 6-10; Reply
4--5.
We disagree with Appellants. As noted above, independent claim 1
recites "powering down at least one of a first subset of the plurality of data
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channels and a first subset of the plurality of data rows in the solid state
memory device that provide the first subset of the plurality of intersections."
Applying the broadest reasonable interpretation in light of the Specification,
this claim limitation only requires the powering down of either a plurality of
data channels or a first subset of the plurality of data rows, not both (i.e., "at
least one of' the two things). The Examiner finds that Cho's solid state
memory device comprising a data storage array having a plurality of
channels each containing solid state storage units and the powering down
one of the data channels while providing power to the other teaches
powering down at least one of a first subset of the plurality of data channels.
Final Act. 2-3 (citing Cho, Figs. 1, 2 (step S105)). We agree with the
Examiner's finding because Cho teaches reducing the number of channels
receiving power, and, therefore, Cho discloses the claimed powering down
of the plurality of data channels. See Cho, Fig. 2, i-f 53 (describing Fig. 2).
Thus, we are not persuaded by Appellants that the Examiner erred in finding
that, under the broadest reasonable interpretation, Cho discloses:
powering down at least one of a first subset of the plurality
of data channels and a first subset of the plurality of data rows in
the solid state memory device that provide the first subset of the
plurality of intersections, and providing power to the second
subset of the plurality of intersections,
as recited in claim 1.
Appellants further contend that the combination of Cho and Tanaka
does not teach powering down at least one of a first subset of a plurality of
data channels and a first subset of a plurality of data rows in a solid state
memory device as required in claim 1 because (1) Tanaka teaches saving
power by having each flash memory device within the array of devices
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adjust individually its own power consumption mode without adjusting the
power of the other devices in its row or channel, and (2) Cho teaches
powering down the memory devices in a data channel. App. Br. 10 (citing
Tanaka, Fig. 4, i-fi-1 66, 107, 111 ); Reply Br. 4. Appellants contend that each
of the references essentially teaches "adjusting the power to a single, linear
grouping of memory devices," instead of the claimed subset of data channels
and rows. Reply Br. 4.
We do not find Appellants' contentions persuasive because they fail to
address the specific findings of the Examiner based upon the combination of
Cho and Tanaka. That is, Appellants attack Tanaka and Cho individually for
failing to disclose powering down at least one of a first subset of the
plurality of data channels and a first subset of the plurality of data rows in
the solid state memory device that provide the first subset of the plurality of
intersections, and providing power to the second subset of the plurality of
intersections, whereas the Examiner relies on the combination of Cho and
Tanaka to teach the disputed limitation.
The Examiner finds that Cho teaches a solid state memory device and
powering down one data channel of the device. Final Act. 2-3 (citing Cho,
Figs. 1, 2). The Examiner then finds that Tanaka teaches a solid state
storage unit comprising a plurality of data channels intersecting a plurality of
data rows with solid state storage located at the intersections, and that
powering down each flash memory module in a RAID (Redundant Arrays of
Inexpensive Disks) group in Tanaka teaches powering down a first subset of
a plurality of data rows. Id. at 3--4 (citing Tanaka, Fig. 1 ); Ans. 3. The
Examiner finds that powering down the flash memory modules in Tanaka's
RAID group teaches powering down a first subset of a plurality of data rows
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because all of the memory elements of a RAID group are aligned in a row.
Final Act. 4; Ans. 3. The Examiner then concludes that it would have been
obvious to one of ordinary skill in the art to combine the teachings of Cho
with Tanaka's teaching of an intersecting channel and row structure "in
order to conserve the power consumption in the flash memory controller."
Final Act. 4. Thus, the Examiner relies upon the combination of Cho's
teaching of powering down at least one of a first subset of a plurality of data
channels and Tanaka's teaching of powering down at least one of a first
subset of a plurality of data rows, each within a solid state memory device.
Accordingly, Appellants' contentions do not persuade us of error on
the part of the Examiner because Appellants are responding to the rejection
by attacking the references separately, even though the rejection is based on
the combined teachings of the references. Nonobviousness cannot be
established by attacking the references individually when the rejection is
predicated upon a combination of prior art disclosures. See In re Merck &
Co. Inc., 800 F.2d 1091, 1097 (Fed. Cir. 1986).
Accordingly, we sustain the Examiner's rejection of independent
claims 1, 8, and 15, as well as dependent claims 2, 3, 5-7, 9, 10, 12-14, 16,
17, 19, and 20, which are not argued separately.
Claim 4, 11, and 18
Dependent claim 4 recites a solid state drive that includes a plurality
of solid state data storage units that are solid state chips. Dependent claims
11 and 18 recite similar limitations. The Examiner finds that Tanaka's
RAID groups containing memory modules of flash memory chips teaches
the claimed solid state drive because Tanaka's modules contain flash
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memory chips that are solid state chips. Ans. 3--4. In response to the
Examiner's finding, Appellants contend that Tanaka does not teach the
claimed solid state drive because the RAID groups of Tanaka do not fit
within the broadest reasonable interpretation of a "solid state drive." Reply
5.
We disagree with Appellants. Under the broadest reasonable
interpretation, we agree with the Examiner that "solid state data storage
units" that are "solid state chip[ s ]" encompasses "flash memory modules
containing flash memory chips." See Ans. 4. Appellants fail to provide
persuasive argument or evidence to rebut this finding of the Examiner.
Accordingly, we disagree with Appellants that Tanaka fails to disclose the
limitation that "the solid state memory device is a solid state drive and each
of the plurality of solid state data storage units is a solid state chip."
Appellants further contend that dependent claims 4, 11, and 18 are
allowable for the same reasons as independent claim 1. App. Br. 11. We are
not persuaded by this argument for the same reasons set forth above with
respect to claim 1.
Accordingly, we sustain the Examiner's rejection of dependent claims
4, 11, and 18.
CONCLUSION
The Examiner did not err in rejecting claims 1-20 under 35 U.S.C.
§ 103(a) as obvious over Cho and Tanaka.
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DECISION
To summarize, the rejection of claims 1-20 under 35 U.S.C. § 103(a)
as obvious over Cho and Tanaka is affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(l )(iv).
AFFIRMED
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