Ex Parte Engh-Halstvedt et al

Patent Trial and Appeal Board

Oct 5, 2017

13459347 (P.T.A.B. Oct. 5, 2017)

United States Patent and Trademark Office
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O.Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
13/459,347 04/30/2012 Andreas Due ENGH-HALSTVEDT SCS-550-1507 1296
73459 7590 10/10/2017
NIXON & VANDERHYE, P.C.
901 NORTH GLEBE ROAD, 11TH FLOOR
ARLINGTON, VA 22203
EXAMINER
LI, SIDNEY
ART UNIT PAPER NUMBER
2136
NOTIFICATION DATE DELIVERY MODE
10/10/2017 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
PTOMAIL@nixonvan.com
pair_nixon @ firsttofile. com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte ANDREAS DUE ENGH-HALSTVEDT and JORN NYSTAD
Appeal 2017-003365
Application 13/459,347
Technology Center 2100
Before THU A. DANG, WILLIAM M. FINK, and
STEVEN M. AMUNDSON, Administrative Patent Judges.
AMUNDSON, Administrative Patent Judge.
DECISION ON APPEAL
Appellants1 seek our review under 35 U.S.C. § 134(a) from a final
rejection of claims 1 and 3—17, i.e., all pending claims. We have jurisdiction
under 35 U.S.C. § 6(b).
We reverse.
STATEMENT OF THE CASE
The Invention
According to the Specification, the invention “relates to data
processing systems including processing pipelines and to the control of the
appellants identify the real party in interest as ARM Limited. App. Br. 3.
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Application 13/459,347
processing pipelines within such data processing systems.” Spec. 2:3—5.2
The Specification explains that the invention “provides a processing
pipeline” having “a first pipeline portion and a second pipeline portion” and
“includes two loops, one formed by the first pipeline portion and one formed
by the second pipeline portion.” Id. at 3:17—30. The Specification further
explains that a “subject instruction recirculates within the first pipeline
portion until the target data for that subject instruction is stored within the
cache,” and once the cache contains the target data, “the subject instruction
is released in to the second pipeline portion within which it can recirculate,
if necessary, until the further processing operations performed by that
second pipeline portion are completed and the subject instruction retired.”
Id. at 3:30-4:3.
Exemplary Claim
Independent claim 1 exemplifies the claims at issue and reads as
follows:
1. Apparatus for processing data comprising:
a memory configured to store data;
a cache configured to store data fetched from said
memory; and
a processing pipeline having a plurality of pipeline stages
and configured to perform data processing operations specified
by program instructions passing along said processing pipeline,
wherein
2 This decision uses the following abbreviations: “Spec.” for the
Specification, filed April 30, 2012; “Final Act.” for the Final Office Action,
mailed February 3, 2016; “App. Br.” for the Appeal Brief, filed July 5, 2016;
“Ans.” for the Examiner’s Answer, mailed November 2, 2016; and
“Reply Br.” for the Reply Brief, filed December 28, 2016.
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Application 13/459,347
said processing pipeline comprises a first pipeline portion
having a plurality of pipeline stages followed by a second
pipeline portion having a plurality of pipeline stages;
said first pipeline portion includes a load stage
configured to respond to a subject instruction using target data,
when said target data is not already stored within said cache, by
fetching said target data from said memory and storing said
target data within said cache;
said first pipeline portion includes a first gating stage
following said load stage and configured to determine if said
target data is present within said cache and:
(i) if said target data is not present within said
cache, then to recirculate said subject instruction through
said first pipeline portion; and
(ii) if said target data is present within said cache,
then to pass said subject instruction to said second
pipeline portion;
said second pipeline portion includes a further processing
stage configured to respond to said subject instruction by
performing a further processing operation using said target data;
and
said second pipeline portion includes a second gating
stage following said further processing stage and configured to
determine if said further processing operation is completed and:
(i) if said further processing operation is not
completed, then to recirculate said subject instruction
through said second pipeline portion; and
(ii) if said further processing operation is
completed, then to retire said subject instruction from
said processing pipeline,
wherein said target data is locked within said cache until
all program instructions that use said target data have been
retired from said processing pipeline.
App. Br. 17—18 (Claims App.).
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Application 13/459,347
The Prior Art Supporting the Rejections on Appeal
As evidence of unpatentability, the Examiner relies on the following
prior art:
Gossett et al.
(“Gossett ’413”)
Gossett et al.
(“Gossett ’460”)
Robinson et al.
(“Robinson”)
Wei et al. (“Wei”)
US 6,236,413 B1 May 22, 2001
US 6,259,460 B1 July 10, 2001
US 2004/0083341 Al Apr. 29, 2004
US 2008/0150949 Al June 26, 2008
The Rejections on Appeal
Claims 1, 3—13, and 15—17 stand rejected under 35 U.S.C. § 103(a) as
unpatentable over Gossett ’460, Gossett ’413, and Robinson. Final
Act. 3-15.
Claim 14 stands rejected under 35 U.S.C. § 103(a) as unpatentable
over Gossett ’460, Gossett ’413, Robinson, and Wei. Final Act. 15—16.
ANAFYSIS
We have reviewed the rejections of claims 1 and 3—17 in light of
Appellants’ arguments that the Examiner erred. Based on the record before
us and for the reasons explained below, we concur with Appellants’
contention that the Examiner erred in the rejections of the claims under
§ 103(a).
The § 103(a) Rejection of Claims 1, 3—13, and 15—17
Appellants argue that the Examiner erred in the rejection of
independent claims 1,16, and 17 because the references do not teach or
suggest “wherein said target data is locked within said cache until all
program instructions that use said target data have been retired from said
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Application 13/459,347
processing pipeline,” as recited in claim 1 and similarly recited in claims 16
and 17. See App. Br. 11—15. More specifically, Appellants assert that
“[t]his feature is missing from” Gossett ’460 and Gossett ’413. Id. at 11—12.
Appellants further assert that Robinson discloses locking cache data based
on a “static” value, i.e., “a predetermined number of accesses or a
predetermined number of misses.” Id. at 13—14 (citing Robinson 113).
Appellants then contend that Robinson’s “static” approach differs from the
claimed “dynamic” approach requiring locking “for the length of time
necessary for [the] instructions” using the locked data to retire. Id. at 14; see
Reply Br. 5. Appellants also contend that “one of ordinary skill in the art
[would not] have been motivated to lock . . . data in Robinson’s cache until
all instructions that use that. . . data are retired” due to Robinson’s “static”
approach. App. Br. 15.
In response, as an initial matter, the Examiner finds that Robinson
“shows a period for which data should remained locked,” i.e., “a
predetermined number of accesses or a predetermined number of misses.”
Ans. 18—19. According to the Examiner, “[b]eing locked for a
predetermined amount of time would include applicant’s limitation of ‘until
all programs instructions that use the target data have been retired from the
processing pipeline’.” Id. at 20. We disagree. Being locked for a “static”
predetermined time, as disclosed in the cited portion of Robinson, would not
necessarily include the time for “all program instructions that use the target
data have been retired.” See Reply 3.
In addition, the Examiner determines that “[o]ne of ordinary skill in
the art would readily be able to set the predetermined static value to a value
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that it takes for all the program instructions in the pipeline to retire.” Id.
at 22-23.
Appellants argue that the Examiner’s determination regarding one of
ordinary skill in the art constitutes “a conclusory statement with no
supporting reasoning, facts, or evidence.” Reply Br. 3. Appellants explain
that because the claims permit instruction recirculation “the actual length of
time the individual instructions spend within the processing pipeline before
they are retired can vary significantly,'1'’ i.e., “from a few cycles to many
cycles.” Id. at 3—5; see App. Br. 14. Appellants assert that a selected long
predetermined locking time (1) “would not be sufficient in all cases” and
(2) “would be hugely detrimental to the overall performance because it
would cause data to be locked in the cache for much longer than is actually
required for normal operations.” Id. at 5.
Based on the record before us, we agree with Appellants that the
Examiner has not adequately explained why one of ordinary skill in the art
would have modified Robinson’s locking duration based on “a
predetermined number” to achieve the claimed locking duration based on
instruction retirement as the claims require. Hence, we do not sustain the
§ 103(a) rejection of claims 1, 16, and 17 based on Gossett ’460,
Gossett ’413, and Robinson.
Claims 3—13 and 15 depend directly or indirectly from claim 1. For
the reasons discussed regarding claim 1, we do not sustain the § 103(a)
rejection of these dependent claims based on Gossett ’460, Gossett ’413, and
Robinson.
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The § 103(a) Rejection of Claim 14
Claim 14 depends from claim 1. Based on the record before us, the
Examiner has not shown how the additionally cited Wei reference
overcomes the deficiency discussed above for claim 1. Consequently, we do
not sustain the § 103(a) rejection of claiml4.
DECISION
We reverse the Examiner’s decision rejecting claims 1 and 3—17.
REVERSED
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