Ex Parte Elfadel et al

Patent Trial and Appeal Board

Oct 31, 2014

12267599 (P.T.A.B. Oct. 31, 2014)

UNITED STATES PATENT AND TRADEMARKOFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
12/267,599 11/09/2008 Ibrahim M. Elfadel YOR920080649US1 6517
63919 7590 11/03/2014
MICHAEL J. CHANG, LLC
84 SUMMIT AVENUE
MILFORD, CT 06460
EXAMINER
LIN, SUN J
ART UNIT PAPER NUMBER
2851
MAIL DATE DELIVERY MODE
11/03/2014 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________

Ex parte IBRAMHIM M. ELFADEL and
TAREK A. EL-MOSELHY
____________

Appeal 2012-009867
Application 12/267,599
Technology Center 2800
____________

Before BRADLEY R. GARRIS, PETER F. KRATZ, and
GEORGE C. BEST, Administrative Patent Judges.

KRATZ, Administrative Patent Judge.

DECISION ON APPEAL
This is a decision on an appeal under 35 U.S.C. § 134 from the
Examiner’s final rejection of claims 1–11 and 13–18. We have jurisdiction
pursuant to 35 U.S.C. § 6.
Appellants’ claimed invention is directed to a method, an apparatus,
and an article of manufacture for determining three-dimensional coupling
capacitance between selected conductors in an integrated circuit design. A
three-dimensional representation of the circuit design is generated utilizing
three-dimensional technology and three-dimensional geometric inputs about
the circuit design. Conductors of interest from the circuit design are chosen
for use as the selected conductors. A computing device is employed in at
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least one of the method steps. The three-dimensional technology
information input may “comprise information about three-dimensional
conformal dielectrics” (Spec. ¶ 25).
Claim 1 is illustrative and reproduced below:
1. A computer-implemented method for determining
coupling capacitance between conductors within an integrated
circuit design, the method comprising the steps of:
generating a three-dimensional representation of the
integrated circuit design based on three-dimensional technology
input and three-dimensional geometric input about the
integrated circuit design;
selecting conductors of interest from the integrated
circuit design; and
determining three-dimensional coupling capacitance
between the selected conductors, wherein at least one of the
steps is carried out using a computer device.

The Examiner relies on the following prior art references as evidence
in rejecting the appealed claims:
Batterywala US 2006/0053394 A1 Mar. 9, 2006
Tcherniaev US 7,669,152 B1 Feb. 23, 2010

The Examiner maintains the following grounds of rejection:
Claims 1, 2, 5–11, and 13–18 stand rejected under 35 U.S.C. § 102(b)
as being anticipated by Batterywala. Claims 3 and 4 stand rejected under 35
U.S.C. § 103(a) as being unpatentable over Batterywala in view of
Tcherniaev.
We affirm both rejections for substantially the reasons set forth by the
Examiner.
Concerning the anticipation rejection, Appellants present substantially
the same argument with respect to each of the independent claims 1, 13, and
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16 and do not argue the anticipatorily rejected dependent claims separately
(App. Br. 10–14). Accordingly, we focus on claim 1 as the selected
representative claim in deciding this appeal as to the Examiner’s anticipation
rejection.
Appellants argue that the method of claim 1 differs from the method
described by Batterywala because Batterywala uses two-dimensional
technology input information, including composition information, about a
vertical cross-section of an integrated circuit taken from a technology file in
determining coupling capacitance between conductors of an integrated
circuit whereas a three-dimensional technology input is required by the
method of claim 1 (App. Br. 10–11).
However, we concur with the Examiner’s determination that
Appellants’ argument lacks persuasive merit (Ans. 9). This is because
Batterywala discloses that the information contained in the technology file
includes information about the composition of a vertical cross-section of the
integrated circuit, and further includes sufficient information from which a
set of all dielectric configurations which could be encountered when
conducting random walks, including configurations with more than two
dielectrics, can be identified (Batterywala ¶¶ 0023, 0067).1 In this regard,
information concerning dielectric configurations is three-dimensional
technology information input. Significantly, the claim term “three-
dimensional technology input” embraces information about dielectric
configurations, including those employing multiple dielectrics that may be
encountered in an integrated circuit design (Spec. ¶¶ 0024–0025).

1 A random walk path is illustrated in Figure 3 of Batterywala (see also
Appellants’ Figure 8).
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In addition, we observe that representative claim 1 does not limit the
integrated circuit in a manner that excludes circuit designs that may
comprise relatively non-complex stacked dielectric layers, including wiring
layers, as acknowledged by Appellants to be addressed by Batterywala
(Spec. ¶ 0007). Hence, Appellants’ argument that the stacked layer
arrangement in the cross-section depicted in Figure 1 of Batterywala and the
technology file information related thereto fail to furnish a description of
three-dimensional information is not persuasive of substantive error in the
Examiner’s anticipation determination (Reply Br. 4–7).
On this record, we shall sustain the Examiner’s anticipation rejection.
Concerning the Examiner’s obviousness rejection of dependent claims
3 and 4, Appellants argue the claims together as a group. We select claim 3
as the representative claim on which we focus in deciding this appeal as to
this ground of rejection. Claim 3 depends from claim 1 through claim 2 and
includes the step of “evaluating whether enough random walk paths have
been created to attain the level of accuracy” that is set for determining the
coupling capacitance (claim 3). The Examiner relies on a combination of
Batterywala and Tcherniaev for teaching or suggesting this argued limitation
(Ans. 7–8). Appellants urge that Tcherniaev contains no such teaching
(App. Br. 14; Reply Br. 8).
Contrary to Appellants’ contention, we concur with the Examiner that
Tcherniaev teaches that threshold levels of accuracy can be evaluated for a
coupling parameter such as capacitance and random walk procedures may be
repeated, which teachings reasonably suggest an accuracy evaluation step
corresponding to that required by claim 3, which accuracy evaluation step
would have been obvious for one of ordinary skill in the art to employ in
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evaluating the accuracy of the capacitance coupling parameters estimated by
the procedure of Batterywala (Ans. 9–10; Tcherniaev, col. 6, ll. 32–53, Figs
2, 4).
Accordingly, we shall sustain the Examiner’s separate obviousness
rejection of dependent claims 3 and 4.

CONCLUSION/ORDER
The Examiner’s decision to reject the appealed claims is affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a).

AFFIRMED

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