Ex Parte Elend

Board of Patent Appeals and Interferences

Mar 11, 2009

10502360 (B.P.A.I. Mar. 11, 2009)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________
BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
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Ex parte BERND ELEND
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Appeal 2008-2374
Application 10/502,360
Technology Center 2800
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Decided:1 March 11, 2009
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Before JOHN C. MARTIN, LEE E. BARRETT, and
JOSEPH F. RUGGIERO, Administrative Patent Judges.

BARRETT, Administrative Patent Judge.

DECISION ON APPEAL
This is a decision on appeal under 35 U.S.C. § 134(a) from the final
rejection of claims 1-4. We have jurisdiction under 35 U.S.C. § 6(b).
We affirm.

1 The two-month time period for filing an appeal or commencing a
civil action, as recited in 37 C.F.R. § 1.304, begins to run from the decided
date shown on this page of the decision. The time period does not run from
the Mail Date (paper delivery) or Notification Date (electronic delivery).
Appeal 2008-2374
Application 10/502,360

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STATEMENT OF THE CASE
Appellant's invention
The invention relates to a transmitter output stage for a two-wire bus.
Known two-wire bus systems, such as the CAN (Controller Area Network)
bus, use so-called common mode chokes which are provided separately from
the transmitter output stage to reduce the electromagnetic radiation from the
bus system "by virtue of the fact that the common mode chokes impose
currents of equal size but opposite sign on the two wires of the bus system"
(Spec. 1: 5-6). However, common mode chokes represent an additional cost
because they have to be provided as separate pieces of circuitry.
The transmitter output stage of the invention uses a transistor circuit
to generate equal but opposite currents to the two wires of the bus system.

Claims
The sole independent claim 1 is reproduced below: 2

1. A transmitter output stage for a two-wire bus, which output stage
imposes equal but opposed currents on the two wires (7, 8) of the bus
and has a first voltage source (5) for supplying voltage, a second
voltage or current source (6) for controlling the equal but opposed
currents and for generating data bits on the bus wires (7, 8), and two
first transistors (1, 2) whose bases are driven by the second voltage
source (6) and which both generate equal collector currents of which
one (I1) is fed to the first bus wire (7) and a second (IT1) is fed to an
input of a current mirror circuit (3, 4) that, at the output end, imposes
on the second bus wire (8) a current (I2) that is of equal value but
opposite sign to the current (I1) fed to the first bus wire (7).

2 We presume currents "(I.sub.1)" and "(I.sub.T1)," and "current
(12)" in the copy of claim 1 in the Appendix are meant to be current "(I1),"
"(IT1)," and "current (I2)" as shown in the claim.
Appeal 2008-2374
Application 10/502,360

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References

Cartwright U.S. 4,064,506 Dec. 20, 1977
Van Tran U.S. 4,649,301 Mar. 10, 1987

Rejection
Claims 1-4 stand rejected under 35 U.S.C. § 103(a) as unpatentable
over Van Tran and Cartwright.
The Examiner finds that the sense amplifier of Figure 10 of Van Tran
shows the claimed invention except that the transistors are field effect
transistors (FETs), not bipolar transistors. In particular, the Examiner finds
that Figure 10 of Van Tran "shows a transmitter output stage for a two-wire
bus (drains/emitter of M5 and M4), which output stage imposes equal but
opposed currents on the two wires of the bus" (Final Rej. 2; Ans. 3). The
Examiner finds that ID1 = ID5 because the bases of transistors M1 and M5
are driven by the same voltage, that transistors M2 and M4 form a mirror
circuit which causes ID4 = ID2 = ID1, so ID4 = ID5 (Final Rej. 3-4). The
Examiner finds that since Figure 10 has the same structure as Appellant's
figure, they must have the same operation (Final Rej. 4).
The Examiner finds that Cartwright teaches that bipolar transistors
have an advantage over FETs in that their transconductances tend to be little
affected by emitter-to-collector potential variations and concludes that "it
would have been obvious to one having ordinary skill in the art to replace
Tran's FETs with bipolar transistors for the purpose of improving the circuit
performance" (Final Rej. 2).

Appeal 2008-2374
Application 10/502,360

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Contentions
Appellant argues that the Final Rejection stated: "Appellant argues
that there is no indication in Tran that the output currents [I OUT 1, I OUT 2
of Tran Figure 10] are equal but opposed. The Examiner respectfully
disagrees." (Matter in bracket added by Appellant.) Br. 6. Appellant
disagrees and argues that "the Tran reference itself indicates that the currents
I OUT 1 and I OUT 2 are not in fact equal but opposite" (Br. 6), referring to
column 6, lines 50-51, and column 7, lines 8-9 of Van Tran.
In the Examiner's Answer, the Examiner states that "the rejection
considers Tran's drains/emitters of transistors M5 and M4, which generate
currents ID5 and ID4, as the outputs of transmitter output stage, not the
IOUT 1 and IOUT 2 as stated" (Ans. 4). The Examiner explains why the
output currents ID4 and ID5 would be equal but opposite (Ans. 4-5).

Facts
Figure 10 of Van Tran shows the differential stage 73' and the high
gain stage 76 of the differential sense amplifier of Figure 8 which is
constructed of p-channel and n-channel FETs (field effect transistors).
Van Tran describes that all of the p-channel transistors are identical
and that all of the n-channel transistors are identical (col. 6, ll. 15-17).
Van Tran describes that the transistors are in saturation and that
ID4 = ID2 = ID1 (col. 6, ll. 25-26).
Van Tran describes that Vg1 is the gate-source voltage of
transistor M1 and is set to Vg1 = Vcom + ν (col. 6, ll. 28-29, 34).
Van Tran describes setting Vg5 = Vcom − ν (col. 6, l. 56).

Appeal 2008-2374
Application 10/502,360

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ISSUE
Independent claim 1 does not recite the type of transistor.
Accordingly, Cartwright is not required for the rejection of claim 1.
The issue is: Has Appellant shown error in the Examiner's finding
that Van Tran teaches a two-wire bus having currents of equal value but
opposite sign?

ANALYSIS
The problem on appeal is that Appellant misapprehends what
structure the Examiner considers to correspond to the two-wire bus. The
Examiner finds that Figure 10 of Van Tran "shows a transmitter output stage
for a two-wire bus (drains/emitter of M5 and M4), which output stage
imposes equal but opposed currents on the two wires of the bus" (Final
Rej. 2; Ans. 3). Appellant understood the two-wire bus to be the wires
carrying I OUT 1 and I OUT 2 in Van Tran (Br. 6). The Examiner states
that "the rejection considers Tran's drains/emitters of transistors M5 and M4,
which generate currents ID5 and ID4, as the outputs of transmitter output
stage, not the IOUT 1 and IOUT 2 as stated" (Ans. 4). That is, the Examiner
finds the following portion of the circuit in Figure 10 to correspond to
Appellant's circuit in topology and operation:

Appeal 2008-2374
Application 10/502,360

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Transistors M1, M2, M4, and M5 of Figure 10 of Van Tran are shown
above with a label for current ID2 added.
Appellant's circuit is reproduced below.

Appellant's figure shows two-wire bus 7, 8 having equal but opposite
currents, i.e., I1 = − I2. The Examiner finds that transistors M1, M5, M2,
and M4 in Van Tran correspond (map) to Appellant's transistors 1, 2, 3, and
4, respectively (except for the difference in type of transistor).
Appeal 2008-2374
Application 10/502,360

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Unfortunately, Appellant has not filed a reply brief to respond to the
Examiner's position. We understand how Appellant might assume that the
wires carrying I OUT 1 and I OUT 2 in Van Tran correspond to the two-wire
bus because they are output wires and are drawn horizontally as in
Appellant's figure. However, the Examiner did state that Figure 10 of Van
Tran "shows a transmitter output stage for a two-wire bus (drains/emitter of
M5 and M4), which output stage imposes equal but opposed currents on the
two wires of the bus" (Final Rej. 2; Ans. 3), which we find is sufficient
notice of the Examiner's position. The Examiner corrected Appellant's
misunderstanding in the Examiner's Answer. Now we are faced with the
difficult choice of either concluding that Appellant has shown no error in the
Examiner's rejection or making an unassisted review of the Examiner's
rejection and making Appellant's arguments for him. We have no idea what
Appellant would argue. Would Appellant argue that the currents ID5 and
ID4 in Van Tran are not in a two-wire bus and, if so, how does the definition
of a bus exclude the Examiner's interpretation? Would Appellant argue that
it is improper to look at only part of the circuit in Van Tran and, if so, what
authority is there for such an argument? Would Appellant argue that the
circuit relied upon by the Examiner does not operate as stated and, if so, why
not? These arguments are best made to the Examiner. Accordingly, we
affirm the rejection of claim 1 because Appellant has shown no error in the
Examiner's rejection. Dependent claims 2-4 have not been separately argued
and, thus, the rejection of claims 2-4 is affirmed.
Appeal 2008-2374
Application 10/502,360

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Requests for extensions of time are governed by 37 C.F.R. § 1.136(b).
See 37 C.F.R. § 41.50(f).
AFFIRMED

msc

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