Ex Parte Eisen et al

Patent Trial and Appeal Board

May 31, 2017

13470386 (P.T.A.B. May. 31, 2017)

United States Patent and Trademark Office
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O.Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
13/470,386 05/14/2012 Susan E. Eisen AUS920100510US1 2165
50170 7590 06/01/2017
IBM CORP. (WIP)
c/o WALDER INTELLECTUAL PROPERTY LAW, P.C.
17304 PRESTON ROAD
SUITE 200
DALLAS, TX 75252
EXAMINER
METZGER, MICHAEL J
ART UNIT PAPER NUMBER
2182
MAIL DATE DELIVERY MODE
06/01/2017 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte SUSAN E. EISEN, HUNG Q. LE, BRYAN J. LLOYD,
DUNG Q. NGUYEN, DAVID S. RAY, BENJAMIN W. STOLT, and
SHIH-HSIUNG S. TUNG
Appeal 2017-000058
Application 13/470,3 861
Technology Center 2100
Before ST. JOHN COURTENAY III, JOYCE CRAIG, and
SCOTT E. BAIN, Administrative Patent Judges.
BAIN, Administrative Patent Judge.
DECISION ON APPEAL
Appellants appeal under 35 U.S.C. § 134(a) from the Examiner’s
Final Rejection of claims 1, 5—11, and 15—21, which constitute all claims
pending in the application. Claim 2—\ and 12—14 have been cancelled. We
have jurisdiction under 35 U.S.C. § 6(b).
We AFFIRM.
1 Appellants identify the real parties in interest as International Business
Machines Corporation. App. Br. 2.
Appeal 2017-000058
Application 13/470,386
STATEMENT OF THE CASE
The Claimed Invention
The claimed invention relates to “an improved data processing
apparatus and method,” and more specifically, to “mechanisms for speeding
up the execution of younger store instructions occurring after a
synchronization (sync) instruction.” Spec. 11. Claims 1,11, and 21 are
independent. Claim 1 is illustrative of the invention and the subject matter
of the appeal, and reads as follows (with the disputed limitations
emphasized):
1. A method, in a processor, for executing instructions that
are younger than a previously dispatched synchronization (sync)
instruction, comprising:
dispatching, by an instruction sequencer unit of the
processor, a sync instruction;
sending the sync instruction to a nest of one or more
devices outside of the processor;
dispatching, by the instruction sequencer unit, a
subsequent instruction after dispatching the sync instruction,
wherein the dispatching of the subsequent instruction after
dispatching the sync instruction is performed prior to receiving a
sync acknowledgement response from the nest; and
performing, by the instruction sequencer unit, a
completion of the subsequent instruction based on whether
completion of the subsequent instruction is dependent upon
receiving the sync acknowledgement from the nest and
completion of the sync instruction, wherein the subsequent
instruction is one of a store instruction or a load instruction, and
wherein:
in response to the subsequent instruction being a store
instruction, performing completion of the subsequent instruction
comprises completing execution of the subsequent instruction
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Application 13/470,386
after completion of the sync instruction but prior to receiving the
sync acknowledgement from the nest, and
in response to the subsequent instruction being a load
instruction, performing completion of the subsequent instruction
comprises delaying completion of the execution of the
subsequent instruction until after completion of the sync
instruction and after receiving the sync acknowledgement from
the nest.
App. Br. 18 (Claims App.).
The Rejection on Appeal
Claims 1, 5—11, and 15—21 stand rejected under pre-AIA
35 U.S.C. § 102(b) as being anticipated by Arimilli et al. (US 6,880,073 B2,
issued April 12, 2005) (“Arimilli”). Final Act. 4—13.
ANALYSIS
We have reviewed the Examiner’s rejection in light of Appellants’
arguments presented in this appeal. Arguments which Appellants could
have made but did not make in the Briefs are deemed to be waived. See
37 C.F.R. § 41.37(c)(l)(iv). On the record before us, we are unpersuaded
the Examiner has erred. We adopt as our own the findings and reasons set
forth in the rejections from which the appeal is taken and in the Examiner’s
Answer, and provide the following for highlighting and emphasis.
Appellants argue the Examiner erred in finding Arimilli discloses “in
response to the subsequent instruction being a store instruction, performing
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Appeal 2017-000058
Application 13/470,386
completion of the subsequent instruction,” as recited in claim l.2 App. Br.
5—8 (emphasis added); Reply Br. 2—3. Appellants similarly argue the
Examiner erred in finding Arimilli discloses related claim limitations
reciting the term “completion.” Id. In essence, Appellants’ argument is
directed to the definition of “completion,” which Appellants argue means
(somewhat circularly) “the instruction reaching a completion stage of
processing and completion logic of a processor to perform its operations to
indicate that the instruction has been fully executed and the results of the
instruction have been committed to memory, if any.” App. Br. 6; Reply Br.
2. We, however, are not persuaded of error.
As the Examiner finds, Ans. 17, Appellants’ Specification defines
completion of an instruction as follows: “‘Completion’ of an instruction
means that the instruction is fmish[ed] executing in one of execution units
[within a processor], has passed the point of flushing, and all older
instructions have already been updated in the architecture state, since the
instructions have to be completed in order.” Spec. 1 54. Appellants’
dictionary definition of “completion” (i.e., “concluded”), Reply Br. 4, is
consistent with the foregoing paragraph 54 of the Specification, and adds
nothing further to the understanding of one of ordinary skill in the art
regarding completion of instructions in data processing, as recited in claim 1.
Appellants urge a more restrictive interpretation of the claim term
“completion” based on additional documentary evidence submitted in the
Reply Brief. However, we decline to consider this evidence because it was
2 Appellants argue independent claims 1,11, and 21 as a group, and we
choose claim 1 as representative of the group. See 37 C.F.R.
§ 41.37(c)(l)(iv).
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Application 13/470,386
not timely submitted. See 37 C.F.R. § 41.41(b)(1). Accordingly, giving the
claim its broadest reasonable interpretation in light of the Specification, as
we must, see In re Am. Acad. ofSci. Tech. Ctr., 367 F.3d 1359, 1364 (Fed.
Cir. 2004), we discern no error in the Examiner’s construction of the claim
term “completion.” Ans. 17; Final Act. 4—6. On this record, we are not
persuaded the Examiner’s interpretation is overly broad or unreasonable.3
In light of the foregoing, we also discern no error in the Examiner’s
finding Arimilli discloses the disputed claim limitations, all of which relate
to the relative order of “completion” of instructions. As the Examiner finds,
for example, Arimilli discloses “instructions . . . maintained in issue queues
62-72 until execution of the instructions is complete, and the result data, if
any, are written back to the rename registers.” Ans. 17 (emphasis omitted)
(citing Arimilli col. 6,11. 9-13); see also Arimilli col. 4,11. 38—43, col. 7,11.
4—8; col. 11,11. 11—15. Appellants argue such instructions are not really
“complete” since they are (allegedly) held in a buffer and not as a final
matter “committed” to memory, Reply Br. 8, but we are not persuaded by
this argument for the reasons discussed above.
Similarly, Appellants argue that the system described in Arimilli is
limited to “speculative execution,” whereby “the main idea is to do
[processing] work before it is known whether than work will be needed.”
Reply Br. 8. By its nature, Appellants argue, “speculative execution” cannot
disclose the “completion” of instructions as recited in claim 1. App. Br. 18.
3 Because “applicants may amend claims to narrow their scope, a broad
construction during prosecution creates no unfairness to the applicant or
patentee.” In re ICON Health and Fitness, Inc., 496 F.3d 1374, 1379 (Fed.
Cir. 2007) (citation omitted).
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Again, this argument is premised upon Appellants’ proffered definition of
“completion,” which we reject for the reasons set forth above. As the
Examiner finds, Arimilli discloses “store instructions may be executed prior
to a previous sync acknowledgement,” as required by the claim. Ans. 18
(emphasis added) (citing Arimilli col. 4,11. 38—43; col. 7,11. 4—9). We
discern no error in the Examiner’s finding that “[o]ne of ordinary skill in the
art would understand that execution of a store instruction is finished [i.e.,
complete] when the instruction has sent its data to memory,” as disclosed in
Arimilli. Ans. 18—19.
We find Appellants’ argument regarding the rejection of dependent
claims 5—10 and 15—20 is redundant to the argument regarding the
independent claims. App. Br. 16. See 37 C.F.R. § 41.37(c)(l)(iv).
Therefore, we are not persuaded of error, for the reasons set forth above.
Accordingly, we sustain the rejection of claims 1, 5—11, and 15—21 as
anticipated by Arimilli.
DECISION
We affirm the Examiner’s rejections of claims 1, 5—11, and 15—21.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1). See 37 C.F.R.
§ 41.50(f).
AFFIRMED
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