Ex Parte Eichenberger et al

Patent Trial and Appeal Board

Sep 29, 2016

12834464 (P.T.A.B. Sep. 29, 2016)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE
12/834,464 07/12/2010
75584 7590 09/29/2016
IBM Corp. (WIP)
c/o Walder Intellectual Property Law, P.C.
17304 Preston Road
Suite 200
Dallas, TX 75252
FIRST NAMED INVENTOR
Alexandre E. Eichenberger
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
YOR920100125US1 8543
EXAMINER
CALDWELL, ANDREW T
ART UNIT PAPER NUMBER
2183
MAILDATE DELIVERY MODE
09/29/2016 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte ALEXANDRE E. EICHENBERGER,
MICHAEL K. GSCHWIND, JOHN A. GUNNELS, and
VALENTINA SALAPURA1
Appeal2015-003581
Application 12/834,464
Technology Center 2100
Before KRISTEN L. DROESCH, KAMRAN JIV ANI, and
MATTHEW J. McNEILL, Administrative Patent Judges.
DROESCH, Administrative Patent Judge.
DECISION ON APPEAL
STATEMENT OF THE CASE
Appellants seek review under 35 U.S.C. § 134(a) from the Final
Rejection of claims 1-25, all of the pending claims in the application. We
have jurisdiction under 35 U.S.C. § 6(b ).
We REVERSE.
1 Appellants indicate the real party-in-interest is International Business
Machines Corporation. App. Br. 2.
Appeal2015-003581
Application 12/834,464
BACKGROUND
The disclosed invention relates to a data processing apparatus and
method for implementing matrix multiplication operations using pair-wise
load and splat operations. Spec. i-f 2.
Representative claim 1 reproduced from the Claims Appendix of the
Appeal Brief, reads as follows (disputed limitations in italics):
1. A method, in a data processing system comprising a
processor, for performing a matrix multiplication operation,
compnsmg:
performing, by the processor, a vector load operation to
load a first vector operand of the matrix multiplication
operation to a first target vector register of the data processing
system, the first vector operand comprising one or more values;
performing, by the processor, a load pair and splat operation
by executing a single load pair and splat instruction which loads a
pair of values of a second vector operand into a second target vector
register of the data processing system and replicates the pair of
values within the second target vector register such that the second
target vector register stores at least a first instance of the pair of
values of the second vector operand and a second instance of the pair
of values of the second vector operand;
performing, by the processor, an operation on elements of the
first target vector register and elements of the second target vector
register to generate a partial product of the matrix multiplication
operation;
accumulating, by the processor, the partial product of the matrix
multiplication operation with other partial products of the matrix
multiplication operation to generate a result of the matrix
multiplication operation.
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Appeal2015-003581
Application 12/834,464
REJECTIONS
Claims 1-8, 10-16, and 18-24 stand rejected under 35 U.S.C.
§ 102(e) as anticipated by Mimar (US 7,873,812 Bl; issued Jan. 18, 2011),
as evidenced by ALTIVECâ„¢ TECHNOLOGY PROGRAMMING INTERFACE
MANUAL, Freescale Semiconductor, 1999 ("Freescale").
Claims 9, 17, and 25 stand rejected under 35 U.S.C. § 103(a) as
unpatentable over Mimar and Liu et al. (US 2007/0198815 Al; published
Aug. 23, 2007).
ANALYSIS
We have reviewed the Examiner's rejection in light of Appellants'
arguments in the Appeal Brief, the Examiner's Answer, and the arguments
in the Reply Brief. We agree with Appellants' arguments. We highlight and
address specific findings and arguments below for emphasis.
The Examiner finds that Mimar discloses a load pair and splat
operation, as recited in independent claims 1, l 0, and 18. See Final Act. 4
(citing Mimar 3 :25-30, Fig. 1 O; Freescale vector permute instruction). The
Examiner further explains: "[t]he 'splat operation is the act of loading a
single value multiple times into the target vector." Ans. 18. The Examiner
produces an exemplary illustration and asserts "[b ]oth values [(i.e., IO, I4)]
are 'splatted' by loading the same values into the resultant vector multiple
times." Id.
Appellants contend the Freescale permute instruction is not equivalent
to the claimed load pair and splat instruction because it does not perform
loading a pair of values of an operand and replicating the pair of values
within the target vector register, but describes a permute instruction which
shifts values within a vector. See App. Br. 7-8, 11 (citing Mimar 3 :24--34,
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Appeal2015-003581
Application 12/834,464
Fig. 10); Reply Br. 4, 6-7. Appellants argue the vec_perm instruction
merely selects elements independently from the input vectors a and b based
on the index vector c so as to permute the values. See App. Br. 10-11;
Reply Br. 3--4. Appellants further contend the vector permute instruction
loads 16 individual values into the target register d based on the values
specified in each of the slots of the index register c. See Reply Br. 6. Lastly,
Appellants argue that even if one were to consider two of the loads in the
vector permute instruction to be the loading of a pair of values into a target
register, there still is no replication of this pair of values within the target
register. See Reply Br. 6-7.
We agree with Appellants' arguments. In particular, we agree with
Appellants that loading a single value multiple times into a target vector
register, or loading the same values (i.e., IO, I4) into the resultant vector
multiple times as asserted by the Examiner (see Ans. 18) does not disclose,
without more, the replication of the pair of values within the target register
as required by claims 1, 10, and 18. For these reasons, we are constrained to
reverse the Examiner's rejection of claims 1-8, 10-16, and 18-24 as
anticipated by Mimar. As applied by the Examiner (see Final Act. 12-13),
the teachings of Liu do not remedy the deficiencies of Mimar. Accordingly,
for the same reasons as claims 1-8, 10-16, and 18-24, we are constrained to
reverse the Examiner's rejection of dependent claims 9, 17, and 25 as
unpatentable over Mimar and Liu.
DECISION
We REVERSE the rejection of claims 1-25.
REVERSED
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