Ex Parte Duvalsaint et alDownload PDFPatent Trial and Appeal BoardSep 30, 201612275552 (P.T.A.B. Sep. 30, 2016) Copy Citation UNITED STA TES p A TENT AND TRADEMARK OFFICE APPLICATION NO. FILING DATE 12/275,552 11/21/2008 79980 7590 10/04/2016 Keohane & D'Alessandro 1881 Western Avenue Suite 180 Albany, NY 12203 FIRST NAMED INVENTOR KarlJ. Duvalsaint UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www .uspto.gov ATTORNEY DOCKET NO. CONFIRMATION NO. END920080397US 1 2282 EXAMINER MERCADO, RAMON A ART UNIT PAPER NUMBER 2132 NOTIFICATION DATE DELIVERY MODE 10/04/2016 ELECTRONIC Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the following e-mail address( es): drubbone@kdiplaw.com Docket@Kdiplaw.com lcronk@kdiplaw.com PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE BEFORE THE PATENT TRIAL AND APPEAL BOARD Ex parte KARL J. DUVALSAINT, DAEIK KIM, and MOONJ.KIM Appeal2015-002724 Application 12/275,552 Technology Center 2100 Before ROBERT E. NAPPI, CARLA M. KRIVAK, and JEFFREY A. STEPHENS, Administrative Patent Judges. KRIVAK, Administrative Patent Judge. DECISION ON APPEAL Appellants appeal under 35 U.S.C. § 134(a) from a final rejection of claims 1, 2, 4, and 6-20, which are all the claims pending in the application. We have jurisdiction under 35 U.S.C. § 6(b). We affirm. Appeal2015-002724 Application 12/275,552 STATEMENT OF THE CASE Appellants' invention is directed to cache memory sharing that "recovers a logic core whose cache memory block is not operational by sharing cache memory blocks which might already engage other logic cores" (Title (capitalization altered); Abstract). Independent claim 1, reproduced below, is exemplary of the subject matter on appeal. 1. A shared cache memory system, comprising: a first memory unit mounted on a bus; a first cache manager coupled to the first memory unit; a first set of sub-memory units coupled to the first cache manager; and a first set of sub-processing elements coupled to the first set of sub-memory units; and a second cache manager coupled to an input and an output of a second memory unit mounted on the bus, the first cache manager receiving a request for memory content originating from the first set of sub-processing elements, and sharing the request for memor; content to the second cache manager in the case that the first set of sub-memory elements is unable to satisfy the request, the first memory unit is exhibiting a yield below a predetermined threshold, and the following are operational: the first set of sub-memory units, and the first set of sub-processing elements, wherein the second cache manager directs the request to the input of the second memory unit to enable a search of the second memory unit and a second set of sub-memory units coupled to the second memory unit. REFERENCES and REJECTION The Examiner rejected claims 1, 2, 4, and 6-20 under 35 U.S.C. § 103(a) based upon the teachings ofVartti (US 7,260,677 Bl; Aug. 21, 2007) and Thapar ("Scalable Cache Coherence for Shared Memory Multiprocessors," 1-12 (1991)). 2 Appeal2015-002724 Application 12/275,552 ANALYSIS The Examiner finds Vartti discloses all the elements of Appellants' claims except for a distributed network and relies on Thapar for disclosing a distributed directory enabling caches to directly share data among themselves through an interconnection network (Final Act. 3-5). Appellants contend the Examiner erred in finding V artti teaches a first cache manager receiving a request for memory content originating from a first set of sub-processing elements (App. Br. 10-12; Reply Br. 3-5). According to Appellants, Vartti teaches a shared cache logic using SLCs (Second-Level Caches), however, "the SLCs are not the originators of requests for memory content[,] rather, they are responding to such a request" (Reply Br. 3; App. Br. 11 (citing Vartti col. 6, 11. 51---64)). Appellants contend "the original request in Vartti originates from the shared SCD [Storage Coherence Director] above the cache, rather than from the sub- processing elements on a lower level, as in the claimed invention" (Reply Br. 4; App. Br. 11-12 (citing Vartti col. 14, 11. 40---67)). Appellants' arguments do not address the Examiner's specific findings that Vartti' s IPs (Instruction Processors) are a first set of cache sub- processing elements originating a request for memory content, as required by claim 1 (Ans. 9-12 (citing Vartti Fig. 1, IPs 1 lOA-D; col. 6, 1. 42---col. 7, 1. 3). We agree with the Examiner's reasonable findings. Vartti's IPs are "any type of processor ... [and] each IP includes a First-Level Cache (PLC)," thereby teaching a first set of sub-processing elements of a cache memory system as required by claim 1 (see Vartti col. 6, 11. 7-13). Vartti's IPs originate a request for "access to a memory address," thereby teaching a request for memory content originating from the first set of sub-processing 3 Appeal2015-002724 Application 12/275,552 elements as required by the claim (see Vartti col. 6, 11. 42--45). When an IP is unable to satisfy the request (see Vartti col. 6, 11. 46-47), the request is shared with other cache memories in the IP' s processing node (see Vartti col. 6, 11. 24--28and11. 47---64; Fig. 1, processing node 120 managed by a processor node director) and with a "cache memory of a different processing node" (see Vartti col. 7, 11. 6-17). Thus, we agree with the Examiner Vartti teaches a first cache manager receiving a request for memory content originating from the first set of sub-processing elements, and sharing the request for memory content in the case that the first set of sub-memory elements is unable to satisfy the request, as recited in claim 1 (Ans. 12). Appellants' further argument (Reply Br. 3) that Vartti determines whether a recent copy of requested data is stored in a shared cache logic in contrast to Appellants' system-which "is not concerned with determining freshness of data"-is not commensurate with the scope of claim 1, as no such limitation is recited. Appellants also contend V artti does not disclose Appellants' memory unit exhibiting a yield below a predetermined threshold as required by claim 1; rather, Vartti "merely designates that a cache may not be used 'because the cache has been degraded following the occurrence of non-recoverable faults' ... [Vartti's] memory systems simply do not include a cache or the cache is degraded" (Reply Br. 3--4 (citing Vartti col. 14, 11. 37--46)). Although claim 1 recites a first memory unit exhibiting a yield below a predetermined threshold, it does not preclude the first memory unit from being degraded by faults as it does not specify how the yield or the predetermined threshold is determined. Thus, we agree with the Examiner finding that Vartti' s degraded cache suggests a memory unit exhibiting a 4 Appeal2015-002724 Application 12/275,552 yield below a predetermined threshold, as claimed (Ans. 12 (citing Vartti col. 14, 11. 39-41); Final Act. 3--4). Appellants further contend V artti does not disclose sharing the request for memory content to a second cache manager, as required by claim 1 (App. Br. 12; Reply Br. 5). According to Appellants, "Vartti assumes the SLCs can satisfy the request, meanwhile failing to indicate that the presence of a non-recoverable cache in combination with a snoop miss will trigger the sharing of the request to a second cache manager" and Thapar does not cure this deficiency (App. Br. 12 (emphasis added)). However, Appellants do not address the Examiner's rejection, which is based on the combination of Vartti' s hierarchical cache memory system with Thapar' s distributed directory protocol for enabling caches to directly share data among themselves through an interconnection network (Final Act. 5---6 (citing Thapar Abstract, pp. 1-2, 4); Ans. 8-9). Specifically, Appellants do not address the teachings of Thapar at all except to state the reference does not cure the deficiencies of Vartti. In light of the broad terms recited in claim 1 and the arguments presented, Appellants have failed to clearly distinguish the claimed invention over the prior art relied on by the Examiner. Therefore, we sustain the Examiner's rejection of independent claim 1, and dependent claims 2, 4, and 6-9 argued for their dependency on claim 1 (App. Br. 18). Appellants' arguments directed to independent claims 10 and 14 present us with the same issues as independent claim 1 (App. Br. 12-18). Thus, for the same reasons as claim 1, we sustain the rejection of independent claims 10 and 14, and dependent claims 11-13 and 15-20 argued for their dependency on claims 10 and 14 (App. Br. 18). 5 Appeal2015-002724 Application 12/275,552 DECISION The Examiner's decision rejecting claims 1, 2, 4, and 6-20 is affirmed. No time period for taking any subsequent action in connection with this appeal may be extended under 37 C.F.R. § 1.136(a)(l )(iv). AFFIRMED 6 Copy with citationCopy as parenthetical citation