Ex Parte Dutt et al

Board of Patent Appeals and Interferences

Feb 25, 2010

10277503 (B.P.A.I. Feb. 25, 2010)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________

Ex parte BALA DUTT, AJAY KUMAR,
and HANUMANTHA R. SUSARLA
___________

Appeal 2009-003684
Application 10/277,503
Technology Center 2100
____________

Decided: February 25, 2010
____________

Before HOWARD B. BLANKENSHIP, JEAN R. HOMERE, and
ST. JOHN COURTENAY III, Administrative Patent Judges.

COURTENAY, Administrative Patent Judge.

DECISION ON APPEAL

This is a decision on appeal under 35 U.S.C. § 134(a) (2002) from the
Examiner’s rejection of claims 1-6, 8-31, and 33-35. Claims 7 and 32 are
cancelled. We have jurisdiction under 35 U.S.C. § 6(b).
We affirm-in-part.

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STATEMENT OF THE CASE
INVENTION
Appellants’ invention is directed to concurrent execution of software
code in computer systems. (Spec. 1).

ILLUSTRATIVE CLAIM 1
1. A system, comprising:
one or more processors;
a memory coupled to the one or more processors, wherein the memory
is configured to store program instructions executable by the one or more
processors to implement a framework to induce multi-threading, wherein the
framework comprises:
a concurrent code generator configured to receive marked code
comprising sequential code having one or more blocks of code marked for
concurrent execution, wherein each marked block of code is marked by
including a marker method call within the code to suggest the block for
potential concurrent execution, wherein the concurrent code generator is
configured to generate concurrent code from the marked code, wherein the
concurrent code comprises one or more tasks configured for concurrent
execution in place of the one or more marked blocks of code; and

1 We note that the preamble of independent claim 24 is directed to a
“tangible, computer accessible storage medium.” (Claim 24). According to
Appellants’ Specification, a computer accessible storage medium includes
“transmission media or signals such as electrical, electromagnetic, or digital
signals, conveyed via a communication medium such as network and/or a
wireless link. (Spec. Para. [0102]). We will interpret the scope of claim 24
and the associated dependent claims as being limited by the express
language of independent claim 24 to “tangible” storage mediums and/or
media only, thereby excluding the aforementioned “signals.” See In re
Nuijten, 500 F.3d 1346, 1357 (Fed. Cir. 2007) (A claim directed to computer
instructions embodied in a signal is not statutory under 35 U.S.C. § 101).

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a scheduler configured to schedule one or more of the tasks for multi-
threaded execution.
PRIOR ART
The Examiner relies upon the following references as evidence:
Reeve US 5,535,393 Jul. 9, 1996
Keeton, “Using Java 2 Standard Edition”

THE REJECTIONS
1. The Examiner provisionally rejected claims 1, 2, 5, 6, 8, 9, 24,
25, 28, 30, and 33 under the judicially created doctrine of
obviousness-type double patenting as being unpatentable over
claims 19-21, 24, 25, 33-35, 38, and 39 of copending
Application No. 10/277,504.

2. The Examiner provisionally rejected claims 12-14 and 16-21
under the judicially created doctrine of non-statutory
obviousness type double-patenting as being unpatentable over
claims 1, 5-8, and 10-11 of copending Application No.
10/277,504 in view of Keeton.

3. The Examiner rejected claims 1-6 and 8-23 under 35 U.S.C.
§103(a) as being unpatentable over the combination of Reeve
and Keeton.

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4. The Examiner rejected claims 24-31 and 33-35 under 35 U.S.C.
§102(b) as being anticipated by Reeve.

ISSUES
Based upon our review of the administrative record, we have
determined that the following issues are dispositive in this appeal:

Issue 1: Under section § 103, did the Examiner err in finding that the
combination of cited references (notably Reeve) would have taught or
suggested a concurrent code generator . . . configured to generate concurrent
code from the marked code?

Issue 2: Under § 102, did the Examiner err in finding that Reeve
discloses or describes “generating concurrent code from the marked code?”
(Claim 24).
PRINCIPLES OF LAW
Anticipation under § 102
In rejecting claims under 35 U.S.C. § 102, “[a] single prior art
reference that discloses, either expressly or inherently, each limitation of a
claim invalidates that claim by anticipation.” Perricone v. Medicis Pharm.
Corp., 432 F.3d 1368, 1375 (Fed. Cir. 2005) (citing Minn. Mining & Mfg.
Co. v. Johnson & Johnson Orthopaedics, Inc., 976 F.2d 1559, 1565 (Fed.
Cir. 1992)).
Obviousness under § 103
What matters is the objective reach of the claim. If the claim extends
to what is obvious, it is invalid under § 103.” KSR Int’l Co. v. Teleflex, Inc.,
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550 U.S. 398, 419 (2007). To be nonobvious, an improvement must be
“more than the predictable use of prior art elements according to their
established functions.” Id. at 417.

FINDINGS OF FACT
In our analysis infra, we rely on the following findings of fact (FF)
that are supported by the record:

The Reeve Reference
1. Reeve discloses that the program directives allow the user to indicate
opportunities for parallelism. (Col. 17, ll. 41-42; see also col. 7, ll.
21-23, “In addition to conventional programming statements, the
source code can include user-specified directives for parallelization”).
2. Reeve discloses that program directives are in the form of Fortran
comments. When a program directive is present, the compiler 60b
generates calls to Runtime Library 66 to cause the parallel execution
of the loopnest. (Col. 17, ll. 47-51; see also Fig. 3).
3. The parallel section and parallel region directives are generated only
by the user and understood only by the compiler. (Col. 17, ll. 52-54).
4. Reeve discloses that the compilation system 60 generates calls to
runtime routines which will set up and cause parallel execution. (Col.
31, ll. 38-40).
5. Reeve discloses that object code output by the compilation system 60
is linked with Runtime Library 66 by link editor 64 to produce code
suitable for execution on the digital data processor 10. (Col. 7, ll. 47-
50).
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6. Reeve discloses that the final decision whether or not it is worthwhile
to actually execute a loop in parallel is made by the compiler or at
runtime. (Col. 10, ll. 55-57).

ANALYSIS
Provisional obviousness-type double patenting rejections
At the outset, we note that Application No. 10/277,504 was issued as
US Patent No. 7,346,902 on March 18, 2008. In the Reply Brief (filed Mar.
6, 2008), Appellants argue the Examiner has set forth a “new” analysis
which constitutes a new ground of rejection in the Answer. (Reply Br. 2).
However, Appellants did not file a petition to the Technology Center
requesting that the Examiner’s double patenting rejection in the Answer be
designated a new ground of rejection.2 Cf. Manual of Patent Examining
Procedure § 1207.03, Heading IV, “Request For Designation As New
Ground of Rejection.” Moreover, Appellants had the opportunity to respond
to the Examiner’s “new” analysis in the Reply Brief. Because Appellants
have not addressed the merits of the Examiner’s analysis (Ans. 3-5), we
summarily sustain the Examiner’s provisional obviousness-type double
patenting rejections of claims 1, 2, 5, 6, 8, 9, 12-14, 16-21, 24, 25, 28, 30,
and 33.

ISSUE 1
We decide the question of whether the Examiner erred in finding
under § 103 that the combination of cited references (notably Reeve) would

2 We note that Appellants filed a paper purporting to be a terminal
disclaimer on December 14, 2007.
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have taught or suggested a concurrent code generator . . . configured to
generate concurrent code from the marked code. (See claim 1).
The Examiner contends that marked code is received by the Runtime
Library 66 that generates concurrent code from the marked code. (Ans. 16,
last paragraph). Thus, the Examiner is reading the claimed concurrent
generator on Reeve’s runtime library 66. (See also Ans. 7, ll. 1-3; Reeve Fig.
3). The Examiner merely looks to the secondary Keeton reference for
teaching a method call. (Ans. 7).
Based upon our review of the record, we are in general agreement
with Appellants’ arguments regarding this issue. (App. Br. 11-13; see also
Reply Br. 6). We begin our analysis by noting that Reeves discloses the use
of program directives that allow the user to indicate opportunities for
parallelism. (FF 1). We note that a program directive in a source code file
directs the compiler preprocessor to perform an action (e.g., source file
inclusions, conditional includes, macros) prior to the actual compilation of
the source code into object code.
Reeve discloses an embodiment where program directives are in the
form of Fortran comments. (FF 2). The parallel section and parallel region
directives are generated only by the user and understood only by the
compiler. (FF 3). Thus, we find Reeve teaches that the user “marks” portions
of sequential source code for parallel execution using Fortran comments. (FF
1-3).
When a program directive is present, Reeve’s compiler 60b generates
calls to the runtime library 66 (Fig. 3) to cause the parallel execution of the
loopnest. (FF 2). Reeve further discloses that object code output by the
compilation system 60 is linked with runtime library 66 by link editor 64 to
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produce code suitable for execution on the digital data processor 10. (FF 5).
Reeve discloses that the compilation system 60 generates calls to runtime
routines which will set up and cause parallel execution. (FF 4). Reeve also
discloses that the final decision whether or not it is worthwhile to actually
execute a loop in parallel is made by the compiler or at runtime. (Col. 10, ll.
55-57).
Based upon our review of the evidence, we find that Reeve’s runtime
library 66 does not fairly generate concurrent code from marked code, but
rather is merely a collection of preexisting runtime routines that are simply
linked with the object code outputted by compiler 60b by link editor 64 to
result in sequential or parallel code (according to user-supplied program
directives) suitable for execution on digital data processor 10. (FF 5; see also
Reeve’s Fig. 3). Therefore, we find persuasive Appellants’ argument that
Reeve’s “Runtime Library 66 does not generate concurrent code from object
code output by compiler 60, but merely manages its execution.” (Reply Br.
6, § 2).
Further, we do not find, nor has the Examiner established, that
Keeton (which is relied on only for the use of methods) cures the
aforementioned deficiencies of Reeve. We are further persuaded by
Appellants’ argument that substituting method calls for compiler directives
would be problematic, as a method call (that invokes a function) does not
operate in the same manner as a compiler directive that instructs a compiler
preprocessor to perform some action. (App. Br. 13, ¶ 2). We note that
independent claim 12 similarly recites the limitation of “generating
concurrent code from the marked code.” (Claim 1). Accordingly, we reverse
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the Examiner’s § 103 rejection of claims 1 and 12 as well as associated
dependent claims 2-6, 8-11, and 13-23.

ISSUE 2
We decide the question of whether Reeve discloses or describes
“generating concurrent code from the marked code” under § 102. (Claim
24). We note that this issue is essentially identical to that discussed supra
because the Examiner states “see claim 1 rejection” in the rejection of claim
24. (Ans. 14). Thus, the Examiner is reading the claimed function of
“generating concurrent code from the marked code” (claim 24) on the
function(s) performed by Reeve’s runtime library 66. (Ans. 7, ll. 1-3; see
also Ans. 14; Reeve Fig. 3). For the same reasons discussed supra regarding
claims 1 and 12, we find the Examiner has not sufficiently developed the
record to clearly establish how Reeve discloses or describes the limitation of
“generating concurrent code from the marked code,” as recited in claim 24.
In addition, Appellants argue that Reeve fails to disclose “scheduling
one or more of the tasks for multi-threaded execution according to priority
information included with the marker for the corresponding marked block.”
(App. Br. 20). In the rejection of claim 24, the Examiner relies on Reeve’s
order tiling parameter (See Reeve, col. 19, l. 51; see also Ans. 14-15).
However, we find the Examiner fails to respond (in the “Response to
Argument” section) to Appellants’ contention that loop dependency
information is clearly different from priority information. (App. Br. 21, ¶2).
Accordingly, we reverse the Examiner’s anticipation rejection of
claim 24 and associated dependent claims 25-31 and 33-35.

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CONCLUSIONS
Based on the findings of facts and analysis above:
Under section § 103, the Examiner erred in finding that the
combination of cited references (notably Reeve) would have taught or
suggested “a concurrent code generator . . . configured to generate
concurrent code from the marked code.”
Under § 102, the Examiner erred in finding that Reeve discloses or
describes “generating concurrent code from the marked code.”

ORDER
We affirm the Examiner’s provisional obviousness-type double
patenting rejections of claims 1, 2, 5, 6, 8, 9, 12-14, 16-21, 24, 25, 28, 30,
and 33.
We reverse the Examiner’s rejection of claims 1-6 and 8-23 under
35 U.S.C. § 103(a).
We reverse the Examiner’s rejection of claims 24-31 and 33-35 under
35 U.S.C. § 102(b).
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

AFFIRMED-IN-PART

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