Ex Parte Dutt et alDownload PDFPatent Trial and Appeal BoardDec 23, 201614053026 (P.T.A.B. Dec. 23, 2016) Copy Citation United States Patent and Trademark Office UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O.Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 14/053,026 10/14/2013 Debaprosad Dutt L12-017US 1349 29416 7590 12/28/2016 T ATTTTF SFMTmNnnrTOR TORPOR ATTON EXAMINER 111 SW 5th Avenue SIEK, VUTHE Suite 700 Portland, OR 97204 ART UNIT PAPER NUMBER 2851 NOTIFICATION DATE DELIVERY MODE 12/28/2016 ELECTRONIC Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the following e-mail address(es): michael.garrabrants@latticesemi.com patent @ latticesemi. com stephanie.sharrett@latticesemi.com PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE BEFORE THE PATENT TRIAL AND APPEAL BOARD Ex parte DEBAPROSAD DUTT, JAMIE FREED, HARISH VENKATAPPA, PRADEEP LENKA, and MINGHAO NI Appeal 2015-008143 Application 14/053,026 Technology Center 2800 Before PETER F. KRATZ, BEVERLY A. FRANKLIN, and CHRISTOPHER L. OGDEN, Administrative Patent Judges. BEVERLY A. FRANKLIN, Administrative Patent Judge. DECISION ON APPEAL Appellants request our review under 35 U.S.C. § 134 of the Examiner’s decision rejecting claims 1—7, and 9-21. We have jurisdiction over the appeal under 35 U.S.C. § 6(b). Appeal 2015-008143 Application 14/053,026 STATEMENT OF THE CASE Claim 1 is illustrative of Appellants’ subject matter on appeal and is set forth below (with text in bold for emphasis): 1. A method comprising: receiving in a computer system configuration information for a plurality of hardware modules of an embedded hardware block of a programmable logic device (PLD), wherein the configuration information is received from a user of the computer system; generating in the computer system a plurality of models for the plurality of hardware modules, wherein a generated model includes the configuration information received for a hardware module; and merging in the computer system the generated models into a combined model of the hardware block, wherein the combined model includes the configuration information received for the plurality of hardware modules and interconnections specified between the plurality of hardware modules. The Examiner relies on the following prior art references as evidence of unpatentability: Allen Diab US 2008/0134127 A1 US 2010/0241882 A1 June 5, 2008 Sept. 23,2010 2 Appeal 2015-008143 Application 14/053,026 THE REJECTIONS 1. Claims 1—6, 9-16, and 18—21 are rejected under 35 U.S.C. § 102(b) as being anticipated by Allen.1 2. Claims 7 and 17 are rejected under 35 U.S.C. § 103(a) over Allen in view of Diab. ANALYSIS Claim interpretation is in dispute in the instant case regarding the claimed phrase “a plurality of hardware modules of an embedded hardware block of a programmable logic device (PLD).” The Examiner views the plurality of hardware modules of an embedded hardware block and related elements of claim 1 as being disclosed by Allen. Final Act. 5—6. Appellants argue that when the claims are understood in view of the Specification, the correct finding is that Allen does not disclose every element of the claims. Appeal Br. 8. In support of this position, Appellants refer to page 1, lines 24—page 2 line 15 of the Specification (reproduced below with text underlined for emphasis): Programmable logic devices (PLDs) (e.g., field programmable gate arrays (FPGAs)), complex programmable logic devices (CPLDs), field programmable system on a chips (FPSCs), or other types of programmable devices) generally include programmable logic blocks which may be configured to implement various operations. Some PLDs also include configurable embedded hardware to support 1 The Examiner indicates that claims 1-6, 9-16 and 18—21 are rejected in Rejection 1. Ans. 3. 3 Appeal 2015-008143 Application 14/053,026 additional operations. However, conventional approaches to configuring such embedded hardware are often cumbersome and unwieldy. For example, in one approach, embedded hardware and programmable logic blocks may be configured in a shared hardware description language (HDL) hierarchy. However, such a hybrid hardware/programmable logic block HDL hierarchy is complex, time consuming to validate, and may not be easily reused for other applications (e.g., having limited portability). In another approach, multiple embedded hardware resources may be implemented as a shared block that interfaces with programmable logic blocks in other HDL hierarchies. Id. Appellants also refer to other parts of the Specification, including Figure 1 having logic blocks 104 which are programmable logic blocks. Appeal Br. 8. On page 9 of the Appeal Brief, Appellants state: Page 4, Lines 24-30 draws a contrast between such programmable logic blocks and “hard intellectual property (IP) blocks 160 to provide additional functionality (e.g., substantially predetermined functionality provided in hardware which may be configured with less programming than logic blocks 104.) The Specification at P. 1 lines 12-17 explains that “multiple embedded hardware resources may be implemented as a shared block that interfaces with programmable logic blocks in other HDL hierarchies ... such hardware block sharing can be problematic, as changes to the configuration of one or more shared hardware resources in the block can ... affect the interoperation of the hardware resources with many programmable logic blocks.” At Lines 17-21, the Specification further discloses that “Such problems are further compounded when additional vendor-provided logic (e.g., soft intellectual property (IP) core logic implemented in 4 Appeal 2015-008143 Application 14/053,026 the programmable logic blocks of the PLD) is used to interface between the embedded hardware and other user- configured programmable logic blocks. Appellants submit that in view of the aforementioned parts of the Specification, one skilled in the art would have understood that “a plurality of hardware modules of an embedded hardware block of a programmable logic device (PLD)” does not read on or refer to programmable logic blocks, such as LUT-based or gate array based logic (as in Allen), contrary to the Examiner’s stated position. Appeal Br. 9. Appellants further state that a clear distinction is drawn between “soft” IP that, in the context of a PLD, is used to program the programmable logic blocks, and the “hard” (see p. 4, line 26 of the Specification) IP blocks that are configurable. Appeal Br. 9. Appellants further state that claim 1 explicitly makes this distinction by reciting a plurality of hardware modules of an embedded hardware block of a programmable logic device (PLD). Id. As such, Appellants submit that claim 1 requires the embedding of a hardware block with a plurality of hardware modules within a PLD. Id. Appellants point out that the Specification explains that such a PLD also would include programmable logic blocks, such as LUT-based or gate- array based logic. Id. As such, Appellants argue that a plurality of hardware modules of an embedded hardware block cannot be construed as reading simply on a programmable logic block or blocks (according to the Examiner’s position), which can be programmed to implement a particular function or circuit. Appeal Br. 10. The Examiner’s response is set forth on pages 6—13 of the Answer. Essentially, it is the Examiner’s positon that the claims do not recite any 5 Appeal 2015-008143 Application 14/053,026 structure of the hardware modules that are different from the hardware modules as taught by Allen. Ans. 6—9. The Examiner does not fully address the specific reasons presented by Appellants regarding how one skilled in the art would have interpreted the claim limitations in view of the Specification. The Examiner does not discuss how one skilled in the art would have understood the meaning of the claim term to be, in light of the Specification. The Examiner discusses Appellants’ Figure 6 and states that it is similar to Allen’s Figure 6A and 6B. Ans. 9. In reply, Appellants reiterate that the Examiner misinterprets the claim language for the reasons set forth on pages 2—\ of the Reply Brief. Appellants explain how there is a distinction between embedded hardware, which the Examiner overlooks in interpreting the claims. Reply Br. 3. Appellants explain that while the Examiner states that the claims do not distinguish the plurality of hardware modules of an embedded hardware block from Allen’s parameterizable processor core (Ans. 7), to the contrary, the distinction is in the very definition and usage itself. Reply Br. 3. Appellants explain that Allen discloses that a processor core used to configure programmable logic is what would be termed in the industry as “soft IP” (Allen, paras. [0013] and [0014]), which discloses “[d]ynamic generation also allows the delivery of device driver logic onto the programmable hardware .... The logic description . . . can then be automatically synthesized [and downloaded] onto the programmable hardware.” Appellants explain that a hardware description that can be synthesized and downloaded is not an embedded hardware to a person of ordinary skill, and a person of ordinary skill would not reasonably arrive at the Examiner’s interpretation. Id. 6 Appeal 2015-008143 Application 14/053,026 We are persuaded by Appellants stated position for the reasons stated in the record by Appellants. Claim terms are given their broadest reasonable interpretation consistent with the Specification as they would be interpreted by one of ordinary skill in the art. See, e.g., In re Suitco Surface, Inc., 603 F.3d 1255, 1259—60 (Fed. Cir. 2010); In re Translogic Tech. Inc., 504 F.3d 1249, 1256 (Fed. Cir. 2007); In re Morris, 127 F.3d 1048, 1054—55 (Fed. Cir. 1997); In re Zletz, 893 F.2d 319, 321—22 (Fed. Cir. 1989). In the instant case, Appellants adequately explain how one skilled in the art would have interpreted the claims terms, in light of the Specification, while the Examiner’s position is absent such import. We thus interpret the claims according to Appellants’ stated position in the record, and, as such, we reverse the rejection because it does not address every element of the claims. Because the Examiner does not rely upon the additional reference in Rejection 2 to cure the stated deficiencies of Rejection 1, we also reverse Rejection 2. DECISION Each rejection is reversed. ORDER REVERSED 7 Copy with citationCopy as parenthetical citation