Ex Parte Downing et al

Board of Patent Appeals and Interferences

Mar 30, 2010

10746023 (B.P.A.I. Mar. 30, 2010)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________
BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________
Ex parte SYLVIA J. DOWNING,
PAUL A. JOLLY,
and ADAM H. WILEN
____________
Appeal 2009-003127
Application 10/746,0231
Technology Center 2100
____________
Decided: March 30, 2010
____________
Before LEE E. BARRETT, HOWARD B. BLANKENSHIP, and
JAMES R. HUGHES, Administrative Patent Judges.

BARRETT, Administrative Patent Judge.

DECISION ON APPEAL
This is a decision on appeal under 35 U.S.C. § 134(a) from the final
rejection of claims 1-30. We have jurisdiction pursuant to 35 U.S.C. § 6(b).
We affirm-in-part.

1 Filed December 24, 2003, titled "Mapping SDVO Functions From
PCI Express Interface." The real party in interest is Intel Corporation.
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STATEMENT OF THE CASE
The invention
The invention relates to an add-on card to be plugged into a Peripheral
Component Interconnect (PCI) Express connector on a motherboard to
provide serial digital video output (SDVO) functionalities. Spec. ¶ 29.2
The advantages of PCI Express architecture include low pin count,
high speed, serial device-to-device interconnect. It is stated that "[t]here is,
however, no mechanism to make use of a digital display codec using the PCI
Express connector." Spec. ¶ 4. The PCI Express defines only a fixed-
frequency interface with significant packet encoding overheads, whereas
"digital displays need to have variable clocking and transfer rates and need
very little overhead for the transfer of video data." Spec. ¶ 5.
One embodiment of the invention is an add-on card which contains a
SDVO-compatible device that can generate digital display signals to drive a
display monitor. The motherboard typically contains a graphics chipset that
supports SDVO. If the add-on card is plugged into a motherboard that
supports either PCI Express or SDVO through the interface connector, the
add-on card can be used as a digital display path upgrade. Spec. ¶ 29. There
is a card sense signal to differentiate between a SDVO compatible card and a
PCI Express compatible card. Spec. ¶ 30.

2 Paragraph numbers refer to published application
US 2005/0172037.

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The card is shown in Figure 2. The mapper 210 maps PCI Express
functions on the interface connector 170 to SDVO functions. The PCI
Express functions and the SDVO functions can be grouped into several
corresponding groups. The mapper 210 is in essence a pin assignment of the
SDVO functions to the PCI Express pins on the interface connector 170.
Spec. ¶ 32.

Illustrative claim
Claim 1 is reproduced below for illustration:

1. An apparatus comprising:

a first group of signal traces to map transmitter differential pairs
pins in a first group of lanes on an interface connector compatible
with a first interface standard to video output points corresponding to
video output signals of a first video port compatible with a second
interface standard;

a second group of signal traces to map presence detect pins in
the first group of lanes on the interface connector to control signal
points corresponding to control signals of the first video port
compatible with the second interface standard; and

a third group of signal traces to map receiver differential pairs
pins in the first group of lanes on the interface connector to video
input points corresponding to video input signals of the first video
port compatible with the second interface standard.

By way of explanation, the "first interface standard" may be the
PCI Express and the "second interface standard" is the SDVO standard,
although other standards can be used. Spec. ¶ 0035. The "video output
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signals" can be the SDVO red, green, blue, and clock signals. Spec. ¶ 0035.
The "control signals" can be the SDVO control clock and control data
signals. Spec. ¶ 0036. The "video input signals" can be the SDVO clock,
interrupt, and stall signals. Spec. ¶ 0037.

The references

Evoy 6,062,480 May 16, 2000
Meinerth 6,124,865 Sept. 26, 2000
Kobayashi US 2005/0066085 A1 Mar. 24, 2005
(filed Jul. 29, 2004)

The rejections
Claims 1-8, 10-18, 20-28, and 30 stand rejected under 35 U.S.C.
§ 103(a) as unpatentable over Kobayashi and Evoy.
Claims 9, 19, and 29 stand rejected under 35 U.S.C. § 103(a) as
unpatentable over Kobayashi and Evoy, further in view of Meinerth.

CONTENTIONS
The Examiner finds that Kobayashi teaches a PCI Express Interface
which relies on differential pair mapping (¶¶ 0102-0104) to route data
packets between a PCI port and graphics port (¶¶ 0113-0114). Final Office
Action (FOA) 2. The Examiner finds that the first interface standard
corresponds to PCI Express (¶ 0113) and the second interface standard
corresponds to SDVO (¶ 0114). Id. The Examiner finds the differential
pairs in the first group of lanes corresponds to stream 1 (Fig. 1) which goes
to video output points (Fig. 29), the differential pairs in the first group
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corresponds to receiver pins for stream 1 (Fig. 1), and the system having an
interface connector (Fig. 29). FOA 2-3. The Examiner finds that Kobayashi
teaches automatic detection, because it teaches hot-plugging at ¶ 0055, but
does not explicitly disclose pins associated with the function. Id. at 3. The
Examiner finds that Evoy teaches presence detect pins to control signal
points and concludes that one of ordinary skill in the art would have been
motivated to modify Kobayashi with Evoy "in order to properly dock
devices upon insertion in a computer environment." Id.
Appellants argue that Kobayashi and Evoy do not disclose, suggest, or
render obvious the limitations of claim 1. The arguments will be addressed
in detail in the analysis.

ISSUES
Issue 1: Does the combination of Kobayashi and Evoy teach or
suggest all of the limitations of apparatus claim 1, method claim 11, and
system claim 21?
Issue 2: If the answer to Issue 1 is yes, does the combination of
Kobayashi, Evoy, and Meinerth teach or suggest the limitations of claims 9,
19, and 29?

FINDINGS OF FACT
Kobayashi
Kobayashi relates to a data packet stream scheduler. ¶ 0002.
Kobayashi describes a video display system having a video source
coupled to a video sink, or receiver, by way of a packet based digital
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interface. A transmitter unit coupled to the source device receives any
number of packetized video data streams each having associate
stream attributes, such as video format, color depth, etc. The receiver unit is
coupled to the source by way of a data, or main link, and an associated
auxiliary link used, in part, to transfer the stream attribute data from the
source to the receiver prior to the transmission of the data packets by way of
the main link. In this way, the packet headers are used to primarily identify
which data stream a data packet is associated. In this way packet overhead
is substantially reduced, preserving main link bandwidth for multimedia
content. In order to coordinate the transmission of the data in the main link,
a transport stream scheduler schedules any of a number of packetized data
streams over the data link where an auxiliary channel for sending stream
attribute data. ¶ 0046.
For example, Figure 12 shows a representative system having a data
stream scheduler 1202 coupled to a multiplexer 1204 and a data buffer 1206
suitable. The scheduler 1202 combines incoming data streams (S1, S2, and
S3) into a link data stream 1208 in the main data channel 222 using time
division multiplexing to combine data packets P1, P2, and P3.
¶¶ 0078-0079. Stream attributes are sent in the auxiliary channel 224.
Kobayashi shows a bi-directional auxiliary channel 224 having
twisted pair (differential pair) wires connecting a source and a display in
Figure 22, and unidirectional main data channel 222 having twisted pair
(differential pair) wires in Figure 23. The main data channel can carry red,
blue, and green video signals. A connector is shown in Figure 24. ¶ 0104.
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Kobayashi describes that a PCI Express port can be augmented to
become compliant with the requirements of the cross platform interface
which can directly drive a display device either using a motherboard
mounted connector. ¶ 0113. In particular, Kobayashi states: "In situations
where it is not practical to mount the connector on the motherboard, the
signals can be routed through the SDVO slot of the PCI Express
motherboard and brought to the back of the PC using a passive card
connector as shown in FIG. 28." ¶ 0114.

Evoy
Evoy describes a hot docking system in a PCMCIA (Personal
Computer Memory Card International Association) equipped computer
which requires insertion and extraction of expansion cards while the
computer is in operation. Col. 1, ll. 7-11.
Evoy describes the computer has a card detection detector 24 coupled
to connector pins CD1 32 (card detect one) and CD2 (card detect two) 34 so
that when a card 28 is fully inserted the pins are activated. Col. 3, ll. 56-58.
The AND gate 24A combines these signals to indicate that the card is
inserted, which enables the card power supply 16. Col. 3, l. 59 to col. 4, l. 1.

PRINCIPLES OF LAW
"[T]he test [for obviousness] is what the combined teachings of the
references would have suggested to those of ordinary skill in the art."
In re Keller, 642 F.2d 413, 425 (CCPA 1981). A rejection under 35 U.S.C.
§ 103(a) is based on the following factual determinations: (1) the scope and
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content of the prior art; (2) the level of ordinary skill in the art; (3) the
differences between the claimed invention and the prior art; and (4) any
objective indicia of non-obviousness. KSR Int'l Co. v. Teleflex Inc.,
550 U.S. 398, 399 (2007) (citing Graham v. John Deere Co., 383 U.S. 1, 17
(1966)). "[H]owever, the analysis need not seek out precise teachings
directed to the specific subject matter of the challenged claim, for a court
can take account of the inferences and creative steps that a person of
ordinary skill in the art would employ." Id. at 418. "A person of ordinary
skill is also a person of ordinary creativity, not an automaton." Id. at 421.

ANALYSIS
Issue 1
We begin with claim interpretation. Claim 1 is to an apparatus, but
the only structures that we see in the claim are "signal traces," "pins," and an
"interface connector" (a mating connector is not required). Claim 1 does not
require that the signal traces and pins are connected to circuitry that
produces or uses the claimed signals. Thus, we interpret the mapping
limitations, such as "to map transmitter differential pairs pins in a first group
of lanes on an interface connector compatible with a first interface standard
to video output points corresponding to video output signals of a first video
port compatible with a second interface standard," to be merely statements
of intended use of how the pins are to intended be connected, which do not
limit the structure. See In re Stencel, 828 F.2d 751, 754 (Fed. Cir. 1987)
(Whether a statement of "intended purpose constitutes a limitation to the
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claims is, as has long been established, a matter to be determined on the
facts of each case in view of the claimed invention as a whole."); Boehringer
Ingelheim Vetmedica, Inc. v. Schering-Plough Corp., 320 F.3d 1339, 1345
(Fed. Cir. 2003) ("An intended use or purpose usually will not limit the
scope of the claim because such statements usually do no more than define a
context in which the invention operates."); Loctite Corp. v. Ultraseal, Ltd.,
781 F.2d 861, 868 (Fed. Cir. 1985) ("we interpret 'adapted to remain . . .
metal surfaces' as merely language of intended use, not a claim limitation").
Accordingly, claim 1 only requires a connector with pins that are capable of
being mapped from one standard to another.
Claim 11 is a method claim, and the functions there are considered
part of the method and must be given weight. Claim 21 is a system claim,
which includes a graphics chipset on a motherboard, an interface connector
attached to the motherboard and compatible with a first interface standard,
and a card plugged into the interface connector which maps to a second
interface standard. Thus, claim 21 requires connection to actual signals.
Initially, we need a tighter reading of the claim limitations onto
Kobayashi. Kobayashi describes a cable having a set of transmitter
differential pair (i.e., twisted pair) wires from a transmitter on the video
source to a receiver on the display device, one for each of Red (R), Green
(G), and Blue (B) video signals, as shown in Figure 23 and described at
¶ 0104. The cable is connected through a connector shown in Figure 24,
where Main Link Ch0+ and Main Link Ch0- pins correspond to, say the Red
signal, Main Link Ch1+ and Main Link Ch1- pins correspond to, say the
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Green signal, and Main Link Ch2+ and Main Link Ch2- pins correspond to,
say the Blue signal. These are the claimed "video output signals."
Kobayashi does not explain how, if all, the connector pins in Figure 24
correspond to the pins of a PCI Express connector. It appears that Figure 24
is just a generic cable having a main link and an auxiliary link.
It is somewhat unclear what is meant by mapping from "receiver
differential pairs pins in the first group of lanes" to "video input points."
"Receiver differential pairs" sounds like a receiver at the source, but "video
input points" sounds like the receiver differential pairs are sending signals to
the video port, which is consistent with the Specification ¶ 0037. The
Examiner's finding that the "receiver differential pairs pins" match to the
receiver 104 (FOA 3) is inconsistent with the claims because this structure
must be at the source and be mapped "to" the video input points.
Nevertheless, it appears that the Aux.Ch.+ and Aux.Ch.- pins can be
considered to be "video input points corresponding to video input signals of
the first video port" absent a more specific limitation of "video input points."
So far, we have only addressed the first and third group of signals and
said nothing about whether the differential pairs map from a "first interface
standard" to a "second interface standard," as claimed. Appellants argue that
¶ 0114 of Kobayashi describes routing the signals through the SDVO slot on
the PCI Express motherboard, but does not teach using a connector to map
between the two standards. Br. 9. It is argued that this only means that the
motherboard has a slot dedicated for an SDVO interface and does not mean
that the PCI Express port of the motherboard is mapped to SDVO signals.
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Br. 9. The Examiner responds that Kobayashi's statement that "the signals
can be routed through the SDVO slot of the PCI Express motherboard"
(¶ 0114) "does not preclude any of the signals from being routed through a
connector nor recite any exclusivity of a connector in all circumstances or
lack of compatibility therein." Ans. 11. Appellants reply that the Examiner
has not shown where Kobayashi teaches the claimed connector. Reply Br. 5.
We do not find any factual support for a connector mapping between a
PCI Express standard and an SDVO standard (or between any other two
standards). There is no teaching or suggestion that the connector in
Figure 24 of Kobayashi maps from a PCI Express standard to an SDVO
standard (or between any other two standards). The connector can simply be
a means to connect a cable to a circuit board or to another cable, both having
the same standard. Kobayashi's teaching that "the signals can be routed
through the SDVO slot of the PCI Express motherboard" (¶ 0114), states
that there is an SDVO slot, not that there is mapping between PCI Express
signals on the motherboard and SDVO signals. The SDVO slot could be
completely separate and different in structure from any PCI Express slots. If
there was a teaching that the SDVO card used the same slot (socket) as a
PCI Express card, so that it received SDVO signals from the motherboard
through the PCI Express slot (socket), then there would be a suggestion of a
mapping, but this is not the case here. However, as to claim 1, we note that
the apparatus only traces and pins of a connector that are capable of being
mapped from one standard to another and this is shown in Kobayashi.
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Appellants argue that Kobayashi discloses "augmenting" a
PCI Express port using a motherboard mounted connector, "not mapping
transmitter differential pairs pins, presence detect pins, or receiver
differential pairs pins to video output points, control signal points, or video
input points, respectively" (Br. 8), and that "[a]ugmenting is not the same as
mapping," id. While we agree that "augmenting" is not equivalent to
"mapping," augmenting does not necessarily exclude mapping. We decide
on the basis that the Examiner has not shown the claimed mapping of
claims 11 and 21 rather than the argument about augmenting.
The other limitation not discussed so far is the second group of
signals. Appellants also argue that Kobayashi and Evoy do not describe or
suggest the limitation of "a second group of signal traces to map presence
detect pins in the first group of lanes on the interface connector to control
signal points corresponding to control signals of the first video port
compatible with the second interface standard." The Examiner refers to the
card detect pins 32 and 34 in Evoy. FOA 3. Appellants argue that the card
detect pins do not suggest mapping presence detect pins "to control signal
points." Br. 9. Appellants argue that, at best, Evoy only describes presence
detect pins, not any mapping. Reply Br. 5.
We agree with the Examiner that the "card detect pins" in Evoy
correspond to presence detect pins and that it would have been obvious to
add presence detect pins to any card in Kobayashi so that the cards can be
detected for "hot-plugging." As to claim 1, it is sufficient that such presence
detect pins are capable of being mapped to control signals since no actual
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connection to circuitry using the control signals is claimed. However, the
presence detect pins do not meet the claim limitation of claims 11 and 21
because there is no teaching of mapping these pins "to control signal points"
on the card as required by the claim language. Accordingly, for this
additional reason, the combination of Kobayashi and Evoy does not satisfy
the language of claims 11 and 21.
Thus, the apparatus in claim 1 would have been obvious over the
combination of Kobayashi and Evoy because claim 1 only requires structure
capable of being connected to signals of a certain type. However, method
claim 11 and system claim 21 would not have been obvious because the
combination of references does not teach mapping between two standards
and does not teach mapping presence detect pins to control signals.

Issue 2
Claim 4 recites that the second interface standard is compatible with a
serial digital video output (SDVO), and claim 9 depends on claim 4 and
recites that "the video input signals include pairs of input clock signals,
interrupt signals, and stall signals." The Examiner relies on Meinerth.
Appellants argue that Meinerth does not teach the limitations of claim 1 or
the further limitations of claim 9.
Claims 4 and 9 do not add any structure to the structure of claim 1.
The structure is still only traces, pins, and an interface connector capable of
mapping between two interface standards. The connector structure in
Kobayashi, as modified to have additional presence detect pins as taught by
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Evoy, is capable of mapping the signals of claims 4 and 9. Accordingly, we
conclude that claim 9 would have been obvious even without Meinerth.
The Examiner does not rely on Meinerth to cure the deficiencies of
Kobayashi and Evoy as to the independent claims, so the rejection of
claims 19 and 29 must be reversed.

CONCLUSION
Issue 1
The combination of Kobayashi and Evoy teaches or suggests all of the
limitations of claim 1, as interpreted, but not independent claims 11 or 21.
Accordingly, the rejection of claims 1-8 and 10 is affirmed and the rejection
of claims 11-18, 20-28, and 30 is reversed.

Issue 2
The combination of Kobayashi, Evoy, and Meinerth teaches or
suggests the limitations of claim 9 because claim 9 does not add any
structure to claims 1 and 4. However, as to claims 9 and 19, the
combination does not cure the deficiencies in the rejection of parent claims
11 and 21. Accordingly, the rejection of claim 9 is affirmed, and the
rejection of claims 9 and 29 is reversed.

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In summary, the rejections of claims 1-10 under 35 U.S.C. § 103(a)
are affirmed and the rejections of claims 11-30 under § 103(a) are reversed.
Requests for extensions of time are governed by 37 C.F.R. § 1.136(b).
See 37 C.F.R. § 41.50(f).

AFFIRMED-IN-PART

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