Ex Parte Dowf et al

Patent Trial and Appeal Board

Feb 26, 2016

13680369 (P.T.A.B. Feb. 26, 2016)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR
13/680,369 11/19/2012
46429 7590 03/01/2016
CANTOR COLBURN LLP-IBM POUGHKEEPSIE
20 Church Street
22nd Floor
Hartford, CT 06103
EliM. Dowf
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
POU920090001 US2 1941
EXAMINER
VICARY, KEITH E
ART UNIT PAPER NUMBER
2183
NOTIFICATION DATE DELIVERY MODE
03/01/2016 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address( es):
usptopatentmail@cantorcolbum.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte ELIM. DOW, MARIE R. LASER, and JESSIE YU
Appeal2014-003735
Application 13/680,369
Technology Center 2100
Before JEAN R. HOMERE, CAROLYN D. THOMAS, and
SHARON PENICK, Administrative Patent Judges.
THOMAS, Administrative Patent Judge.
DECISION ON APPEAL
Appellants seek our review under 35 U.S.C. § 134(a) of the Examiner
finally rejecting claims 1-5, all the pending claims in the present application.
We have jurisdiction over the appeal under 35 U.S.C. § 6(b ).
We AFFIRM.
The present invention relates generally to a computing device
containing a first and second processor, as well as a scheduler configured to
assign processes to the first or second processor. See Abstract.
Appeal2014-003735
Application 13/680,369
Claim l is illustrative:
1. A method of assigning processes to a first processor or a
second processor in a multiprocessor computing device, the method
compnsmg:
ascertaining that the first processor operates faster and
consumes more power than the second processor;
determining whether a process is now or continues to
operate as a spinlock process, a process with a sleeper bonus, or
another type of process; and
assigning, with a scheduler processor in the
multiprocessor computing device, the process to the second processor
in the event that the process is a spinlock process or a process with a
sleeper bonus, otherwise, assigning the process to the first processor;
wherein the second processor includes only a subset of
instructions contained on the first processor.
Appellants appeal the following rejections:
RI. Claims 1-5 are rejected under 35 U.S.C. § 112, 1st paragraph, as
failing to comply with the written description requirement (Final Act. 3);
and
R2. Claims 1-5 are rejected under 35 U.S.C. § 103(a) as being
unpatentable over Hum (US 2009/0222654 Al, Sept. 3, 2009), Bacon (US
6,247,025 Bl, June 12, 2001), and Aas (Understanding the Linux 2.6.8.1
CPU Scheduler); Silicon Graphics, Inc.; 2/17/2005; 38 pgs. (Final Act. 4--
9).
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Appeal2014-003735
Application 13/680,369
ANALYSIS
Rejection under §112, 1st paragraph
Issue 1: Did the Examiner err in finding that at the time of the
invention Appellants did not have possession of the claimed scheduler
processor?
Appellants contend "[t]his rejection, quite simply, ignores the fact that
in order to make a decision, the scheduler must have processing power"
(App. Br. 3).
The Examiner finds that "[i]f the scheduler was indeed a processor,
then the computer device 200 would necessarily have to include three or
more processors, not two or more processors" as set forth in paragraph 21
(Ans. 9). The Examiner further finds "that one of ordinary skill in the art ...
would still readily recognize that a scheduler does not necessarily have to be
a processor" (id.).
To satisfy the written description requirement, the disclosure must
reasonably convey to skilled artisans that Appellants possessed the claimed
invention as of the filing date. Ariad Pharms., Inc. v. Eli Lilly & Co., 598
F.3d 1336, 1351 (Fed. Cir. 2010) (en bane). However, the written
description requirement under § 112 does not demand ( 1) any particular
form of disclosure, or (2) the Specification recite the claimed invention
verbatim, although a description that merely renders the invention obvious
does not satisfy the requirement. Ariad, 598 F.3d at 1352 (citations
omitted). Adequate written description is not dependent on "the presence or
absence of literal support in the specification for the claim language." In re
Kaslow, 707 F.2d 1366, 1375 (Fed. Cir. 1983) (internal citations omitted).
As such, "a lack of literal support does not, in and of itself, establish a prima
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Appeal2014-003735
Application 13/680,369
facie case for lack of adequate descnptlve support .... " Ex parte Parks, 30
USPQ2d 1234, 1236 (BPAI 1993). "Rather, it is sufficient ifthe
originally-filed disclosure would have conveyed to one having ordinary skill
in the art that an appellant had possession of the concept of what is claimed."
Id.
While we agree with the Examiner that the Specification does not
verbatim disclose a "scheduler processor," we believe, however, that the
portions of the Specification identified by Appellants (see App. Br. 3, citing
Spec. i-f 23), as well as other portions of the Specification, reasonably
convey, implicitly, to one of ordinary skill in the art that Appellant had
possession of the concept of a "scheduler processor." We note that the
Specifications describes that "[ t ]he scheduler 206 is configured to assign
processes from the request queue 208 to either first processor 202 or the
second processor 204" (Spec. i-f 23) and "a programmer may indicate in code
whether a particular process should be assigned to the slower processor" (id.
at i-f 24). Given the aforementioned disclosure, we agree with Appellants
that the scheduler must process data/code, the essence of a processor.
Therefore, we agree with Appellants that the concept of a scheduler
processor is implicitly supported by the Specification.
Accordingly, the rejection of claims 1-5 under 35 U.S.C. § 112, first
paragraph, as failing to comply with the written description requirement is
reversed.
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Appeal2014-003735
Application 13/680,369
Rejection under §103(a)
Issue 2: Did the Examiner err in finding that Hum teaches or suggests
the second processor includes only a subset of instructions contained on the
first processor, as set forth in claim 1?
Appellants contend "[ t ]he word subset ... refers to a set of
instructions that is a smaller (e.g., sub) set ... The Examiner, however, has
stated that an equal set of instructions as taught in Hum, teaches a subset"
(App. Br. 3). Appellants further contend that "Hum states the processors
include the same or a partial overlap of instructions [and] [ t ]he partial
overlap indicates that the second processor includes additional instructions"
(id. at 4).
The Examiner finds that "the written description does not appear to
explicitly or implicitly convey that a subset 'refers to a set of instructions
that is a smaller (e.g., sub) set of than those on the first processor ... ' the
specification in no way mandates the interpretation of 'subset' as a 'proper
subset"' (Ans. 11). We agree with the Examiner.
The ordinary and usual meaning of "subset" is a set each of whose
element is an element of an inclusive set. Merriam-Webster's Collegiate
Dictionary, p.117 6 (9th Edition 1990). We find that this broad dictionary
meaning does not prohibit each set from being equal. However, it is well
established that dictionary definitions must give way to the meaning
imparted by the specification, Phillips v. AWH Corp., 415 F.3d 1301 (Fed.
Cir. 2005)(en bane), but in this case Appellants themselves gave "subset"
the broad meaning they now criticize. For example, Appellants'
Specification merely states that "the second processor 204 may include a
subset of the general purpose instructions stored on other, faster processors
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Appeal2014-003735
Application 13/680,369
in the system ... this subset may include general purpose instructions such
as atomic test and set instructions or additional instructions not kept on the
primary processor" (i-f 25). In other words, Appellants' Specification not
only fails to convey that a "subset" refers to a set of instructions that is a
smaller set from among the instructions on the first processor (i.e., a proper
subset), but also explicitly indicates that it can include additional instructions
not in the other set.
Therefore, we find that Appellants' contention is not commensurate
with the scope of claim 1, as claim 1, and the specification, fails to mandate
that the "subset" be a smaller set of instructions. Based on the record before
us, we find no error in the Examiner's obviousness rejection of
representative claim 1, and claims 2-5 which were not separately argued.
Accordingly, we sustain the Examiner's rejection of claims 1-5.
DECISION
We reverse the Examiner's§ 112, first paragraph, rejection of claims
1-5.
We affirm the Examiner's§ 103(a) rejection of claims 1-5.
Because at least one rejection encompassing all claims on appeal is
affirmed, the decision of the Examiner is affirmed. All claims on appeal are
unpatentable.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(l )(iv).
AFFIRMED
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