Ex Parte Doing et al

Patent Trial and Appeal Board

Apr 23, 2014

12176386 (P.T.A.B. Apr. 23, 2014)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
12/176,386 07/20/2008 Richard William Doing RPS920040209US3 2523
10584 7590 04/24/2014
Winstead, P.C.
P.O.Box 131851
Dallas, TX 75313
EXAMINER
LI, AIMEE J
ART UNIT PAPER NUMBER
2183
MAIL DATE DELIVERY MODE
04/24/2014 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE PATENT TRIAL AND APPEAL BOARD

____________

Ex parte RICHARD WILLIAM DOING, BRETT OLSSON,
and KENICHI TSUCHIYA
____________

Appeal 2011-010612
Application 12/176,386
Technology Center 2100
____________

Before ROBERT E. NAPPI, BRUCE R. WINSOR, and
LINZY T. McCARTNEY, Administrative Patent Judges.

McCARTNEY, Administrative Patent Judge.

DECISION ON APPEAL
Appellants appeal under 35 U.S.C. § 134(a) the Examiner’s final
rejection of claims 1, 2, 4, 5, 9-11, and 17. Claims 6 and 7 are canceled, and
claims 3, 8, 12-16, and 18 are allowed. We have jurisdiction under 35
U.S.C. § 6(b).
We AFFIRM.
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STATEMENT OF THE CASE
Appellants’ invention relates to “reducing the fetch time of target
instructions of a predicted taken branch instruction.” Spec. 1. Claim 1
illustrates the claimed subject matter:
1. A method for reducing the normal fetch time of a
predicted taken branch instruction comprising the steps of:
accessing an instruction cache to fetch an instruction;
indexing into an entry in a buffer using bits from said
instruction fetched from said instruction cache, wherein said
buffer comprises a plurality of entries, wherein each of said
plurality of entries comprises an address of a branch instruction,
a plurality of instructions beginning at a target address of said
branch instruction, prediction information for any of said
plurality of instructions that are branch instructions and an
address of a next fetch group;
comparing an address of said instruction fetched from
said instruction cache with said address of said branch
instruction in said indexed entry of said buffer; and
selecting said plurality of instructions beginning at said
target address of said branch instruction in said indexed entry of
said buffer if said address of said instruction fetched from said
instruction cache matches with said address of said branch
instruction in said indexed entry of said buffer.
REJECTION
Claims 1, 2, 4, 5, 9-11, and 17 stand rejected under 35 U.S.C. § 103(a)
as unpatentable over McDonald (US 2004/0143709 Al; July 22, 2004) in
view of Grohoski (US 5,794,027; August 11, 1998).
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ISSUES
Appellants’ Appeal Brief presents the following issues1:
1. Does the cited art teach or suggest the “entries,” “comparing,” and
“selecting” limitations recited in claim 1?
2. Does the cited art teach or suggest the “selecting” limitation recited
in claim 2?
3. Does the cited art teach or suggest the “selecting” limitation recited
in claim 4?
4. Does the cited art teach or suggest the “determining” limitation
recited in claim 5?
5. Does the cited art teach or suggest “a second selection mechanism”
as recited in claim 11?
6. Does the cited art teach or suggest the “buffer queue” recited in
claim 17?
7. Did the Examiner provide sufficient supporting rationale for the
obviousness rejections of claims 1, 2, 4, 5, 11, and 17?

1 Appellants’ Reply Brief includes arguments not presented in
Appellants’ Appeal Brief. Appellants have waived these arguments by
failing to raise them in their Appeal Brief. See Ex parte Borden, 93
USPQ2d 1473, 1474 (informative) (“[T]he reply brief [is not] an opportunity
to make arguments that could have been made in the principal brief on
appeal to rebut the Examiner’s rejections . . . .”). See also Becton Dickinson
& Co. v. C.R. Bard, Inc., 922 F.2d 792, 800 (Fed. Cir. 1990) (“[A]n issue
not raised by an appellant in its opening brief . . . is waived.”). Accordingly,
we consider only arguments Appellants properly raised in their Appeal
Brief.
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ANALYSIS
Claim 1
“Entries”
Claim 1 recites a buffer including a “plurality of entries,” each entry
containing the following four components:
(1) “an address of a branch instruction,”
(2) “a plurality of instructions beginning at a target address of
said branch instruction,”
(3) “prediction information for any of said plurality of
instructions that are branch instructions,” and
(4) “an address of a next fetch group.”
The Examiner found McDonald taught the recited “entries.” As
shown in Figure 3 below, McDonald discloses a Branch Target Address
Cache (referred to as a “BTAC”) that includes target address, tag, and
counter arrays:
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Figure 3: BTAC Diagram
Figure 3 shows an address 182 selecting lines in the target address,
tag, and counter arrays. The Examiner found the selected lines constituted a
single “entry,” and determined these lines, when combined with a branch
buffer storing a “plurality of instructions beginning at a target address”
taught by Grohoski, contained the four components recited in claim 1. (Ans.
at 4-6.)
In response, Appellants argue the Examiner’s interpretation of the
recited “entries” is inconsistent with McDonald’s use of the word.
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Appellants note McDonald refers to individual storage elements as “entries”
(for example, target address array entry 312 in Figure 3 above), not multiple
storage elements as interpreted by the Examiner. (See Reply Br. at 1-4.)
Under this narrower interpretation, Appellants contend none of the disclosed
storage elements includes all four of the recited components. (Id.)
Moreover, Appellants seemingly argue even under the Examiner’s
interpretation of “entries,” McDonald neither teaches nor suggests an entry
including the fourth recited component, “an address of a next fetch group.”
(Id. at 4.)
We agree with the Examiner. During prosecution, we give claim
terms their broadest reasonable interpretation in light of the applicant’s
specification. In re Morris, 127 F.3d 1048, 1054 (Fed. Cir. 1997). Here,
Appellants’ specification discloses an illustrative “entry” that includes
multiple entries, each entry generally containing multiple bits. See, e.g.,
Spec. 12 (“BTB entry 400 may include entries 401A-L. Entry 401A may
store bits 0-22 and 27-29 of the branch instruction address. Entry 401B may
store an address of the target address (bits 0-29) . . . .”). Far from precluding
the Examiner’s interpretation of “entry,” the illustrative entry indicates an
“entry” includes more than one storage element. Even absent this
disclosure, Appellants have pointed to nothing in either the claims or their
specification that limits “entry” to a single storage element.
Although prior art such as McDonald can shed light on the meaning of
claim terms, we note the cited art also suggests the broadest reasonable
interpretation of “entry” includes multiple storage elements. Grohoski,
another prior art reference cited by the Examiner, discloses a Branch
Anticipate Buffer (known as a “BAB”) that includes a table of addresses and
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instructions beginning at each address. (Grohoski, Figure 1, col. 3, ll. 56-
67.) Grohoski refers to each line of the table as an “entry.” (See id.) “[T]he
fact that appellants can point to definitions or usages that conform to their
interpretation does not make the PTO’s definition unreasonable when the
PTO can point to other sources that support its interpretation.” Morris, 127
F.3d at 1056.
As for the “address of a next fetch group,” Appellants apparently
contend the cited art does not teach an address of a group of instructions.
(Reply Br. at 4.) Appellants also contend the Examiner’s rejection relies on
a “BTAC write queue,” which Appellants assert the Examiner erroneously
found was part of the BTAC. (App. Br. at 9.)
We disagree. As an initial matter, the Examiner’s Answer made clear
the Examiner’s rejection did not turn on the BTAC write queue being part of
the BTAC. Rather, as explained in the Answer, the Examiner found
McDonald taught fetching multiple instructions at a target address. (Ans. at
4-5, 12); McDonald ¶ 0007 (“[T]he processor must . . . begin fetching
instructions at the target address . . . .” (emphasis added)). The Examiner
also found McDonald disclosed target addresses were stored in the BTAC
and served as “next current fetch addresses.” (Ans. at 4-5, 12.) Based on
these findings, the Examiner concluded the disclosed target addresses were
the next fetch addresses of a group of instructions. (Id. at 12.) Appellants
have not convinced us these findings are erroneous.
“Comparing”
The Examiner determined the combination of McDonald and
Grohoski taught “comparing an address of said instruction fetched from said
instruction cache with said address of said branch instruction in said indexed
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entry of said buffer.” The Examiner found McDonald disclosed comparing
an address with “tags” that each included part of a branch instruction
address. (Ans. at 5.) The Examiner acknowledged McDonald did not teach
the address came from the recited “instruction cache” but found Grohoski
taught fetching instructions from an instruction cache. (Id. at 5-6.)
In their Appeal Brief, Appellants simply argue the Examiner has not
pointed to any language in either McDonald or Grohoski that suggests
fetching an address from an instruction cache. (App. Br. at 10-11.)
Appellants argue for the first time in their Reply Brief that the cited art does
not teach “comparing an address of an instruction fetched with the address
of the branch instruction” or “in the indexed entry of the buffer.” (Reply Br.
at 6-7.)
We agree with the Examiner. First, Appellants essentially argue
neither McDonald nor Grohoski individually teaches or suggests fetching an
address from an instruction cache. But the Examiner determined the
combination of McDonald and Grohoski suggested this limitation, and
Appellants’ cursory arguments have not convinced us the Examiner’s
determination was erroneous. See In re Keller, 642 F.2d 413, 426 (CCPA
1981) (“[O]ne cannot show non-obviousness by attacking references
individually where, as here, the rejections are based on combinations of
references.”). Second, as alluded to earlier, Appellants have waived their
remaining arguments concerning this limitation because Appellants failed to
raise the arguments in the Appeal Brief. See Borden, 93 USPQ2d at 1474;
Becton Dickinson & Co., 922 F.2d at 800. Regardless, we note that these
arguments are meritless. As explained by the Examiner, McDonald
discloses comparing an address with tags that contain branch instruction
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addresses. (See, e.g., Ans. at 5.) We agree this disclosure, combined with
the teachings of Grohoski, suggests this limitation.
“Selecting”
The Examiner found the combination of McDonald and Grohoski
suggested the “selecting” step recited in claim 1. Appellants argue the cited
combination does not teach or suggest selecting anything “if said address of
said instruction fetched from said instruction cache matches with said
address of said branch instruction in said indexed entry of said buffer” as
recited in claim 1. (App. Br. at 11-14.)
The use of the conditional word “if” makes the “selecting” limitation
optional; therefore, this limitation is not entitled to patentable weight and the
Examiner need not find prior art that teaches this limitation. Cf. Ex Parte
Katz, 2010-006083, 2011 WL 514314, at *4-5 (BPAI 2011) (non-
precedential) (concluding that, under the broadest reasonable interpretation
of the claim at issue, an examiner was not required to find an “if” limitation
in the prior art). Accordingly, we affirm the Examiner’s rejection of claim
1. We note, however, that we agree with the Examiner the combination of
McDonald and Grohoski suggests the limitation for the reasons set forth in
the Examiner’s Final Rejection and Answer.
Claims 2 and 4
Claims 2 and 4 recite selecting an instruction or information,
respectively, “if” a specified condition occurs. Appellants contend the
combination of McDonald and Grohoski neither teaches nor suggests these
limitations. (App. Br. at 14-21.) As with the “selecting” limitation in claim
1, these limitations are optional and therefore the Examiner need not find
these limitations in the prior art. Cf. Katz, 2011 WL 514314, at *4-5. Thus,
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even if Appellants were correct the cited art failed to teach or suggest these
limitations, we would not be persuaded the Examiner’s rejection of these
claims was erroneous.
Claim 5
Claim 5 recites “determining if any of said plurality of instructions
selected is a branch instruction.” The Examiner found the combination of
McDonald and Grohoski disclosed the recited subject matter, in particular
Figure 3D of Grohoski. (Ans. at 7.)
Appellants argue the Examiner overlooked the recited “said plurality
of instructions” are “select[ed] said plurality of instructions beginning at said
target address of said branch instruction in said indexed entry of said
buffer,” as claim 5 depends from—and therefore incorporates the limitations
of—claim 1. Appellants contend Grohoski does not teach or suggest this
limitation. (App. Br. at 19-21.)
We agree with the Examiner. Because claim 5’s “determining” step
depends upon claim 1’s “selecting” step occurring, Appellants correctly
argue the “selecting” step is entitled to patentable weight when considering
claim 5. But as noted above, the Examiner found the combination of
McDonald and Grohoski suggested the “selecting” limitation recited in
claim 1. The Examiner also found step 101 of Grohoski’s Figure 3D
discloses a decision branch that determines whether an instruction is a
branch instruction. (See Grohoski, Figure 3D.) The description
accompanying Figure 3D teaches comparing a branch target address to the
BAB, and if the address is in the BAB, copying the contents of the BAB into
a sequential buffer. (Id. at col. 6, ll. 52-55.) If the system has not resolved
the branch instruction, the system determines whether the next instruction in
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the sequential buffer is a branch instruction. (Id. at col. 7, ll. 2-7.) We see
no error in the Examiner’s finding that these teachings suggest the disputed
limitation.
Claim 11
Claim 11 recites “a second selection mechanism coupled to said first
selection mechanism, wherein said second selection mechanism is
configured to select an address of one of said plurality of instructions
selected to be loaded into an instruction queue.” The Examiner found
Grohoski disclosed an instruction fetch mechanism that suggested this
limitation, in particular, the instruction cache, BAB, and target buffer of the
mechanism. (Ans. at 8.) Figure 2 of Grohoski illustrates an embodiment of
the mechanism:

Figure 2: Block Diagram of an Instruction Fetch Mechanism
Appellants argue the cited art does not teach a “second selection
mechanism coupled to the first selection mechanism” or “where the second
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selection mechanism is configured to select an address of one of the plurality
of instructions selected to be loaded into an instruction queue.” (App. Br. at
21-22.) Moreover, Appellants contend the Examiner has not clarified which
of the target buffer and sequential buffer shown in Figure 2 serves as the
claimed first and second “selection mechanisms.” (Id. at 22.)
Appellants misapprehend the Examiner’s rejection. As explained in
the Examiner’s Final Rejection, the Examiner found the target buffer was
the recited “instruction queue” and the instruction cache and BAB were the
first and second “selection mechanisms.” (Ans. at 8, 18.) As also noted by
the Examiner, the BAB can place selected instructions in either the target or
the sequential buffers. (Id. at 18.) We agree with the Examiner that this
mechanism teaches the claimed subject matter.
Claim 17
Claim 17 recites “a buffer queue coupled to said buffer, wherein said
buffer queue is configured to store instructions selected from said instruction
cache, wherein said buffer queue is further configured to store prediction
information selected from a branch history table.” The Examiner found the
proposed McDonald-Grohoski combination suggested this limitation,
specifically the sequential buffer, BAB, instruction cache, and target buffer
depicted in Figure 2 of Grohoski. (Ans. at 9.)
Appellants contend Grohoski does not disclose the sequential buffer
shown in Figure 2 is configured to store prediction information selected
from the target buffer. (App. Br. at 24.)
Appellants again argue against the cited references individually, but
the Examiner determined the combination of McDonald and Grohoski
suggested the limitations recited in claim 17. The Examiner found that
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McDonald disclosed that target address array entries included prediction
information, (Ans. at 4, 7-8), and concluded the combined McDonald-
Grohoski system would store those entries and their associated prediction
information in the sequential buffer, (id.). Appellants have not persuaded us
this finding is erroneous.
Motivation to Combine
The Examiner found that one of ordinary skill in the art would have
been motivated to combine McDonald and Grohoski in the proposed manner
“for the purpose of improving the overall system performance . . . by
minimizing processor idle time during instruction cache miss or branch
misprediction.” (Ans. at 6.) The Examiner also found Appellants’ alleged
invention was simply a combination of familiar components using known
methods that yielded predictable results, and the combination was obvious to
try. (Id. at 19-23.)
Appellants attack this finding on a number of grounds: Appellants
contend the Examiner’s motivation stems from a misstatement of Grohoski.
(See, e.g., App. Br. at 27.) Appellants argue the Examiner failed to explain
why Grohoski, when accurately read, would motivate one of skill in the art
to make the proposed changes. (Id.) Moreover, Appellants contend the
Examiner failed to make a number of factual findings Appellants believe are
necessary to support the obviousness rejection. (See, e.g., id. at 30, 33-34.)
Appellants also argue the proposed modifications would change
McDonald’s principle of operation. (Id. at 34-35.)
Appellants’ arguments are unpersuasive. First, the Examiner did not
misstate Grohoski. Rather, as indicated by the “see” signal used by the
Examiner, the Examiner inferred from Grohoski’s “objects of the invention”
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statements that Grohoski’s system also aimed to minimize idle time during
instruction cache reloading when a cache miss or misprediction occurs.
(See, e.g., Ans. at 6.) Other portions of Grohoski support this inference.
(See, e.g., Grohoski col. 6, ll. 55-61 (“This provides a temporary storage for
the sequential buffer’s contents in the event that the branch prediction logic
proves to be wrong . . . . This again shows how the BAB improves
performance by immediately providing an instruction stream to the
sequential buffer without having to access the I-cache.” (emphasis added)));
(see also id. at col. 2, l. 56 – col. 3, l. 13.) Other than pointing out the
Examiner did not quote Grohoski, Appellants have not seriously challenged
this finding.
Second, the Examiner provided “articulated reasoning with some
rational underpinning” to support the obviousness rejection. The Examiner
found McDonald and Grohoski disclosed similar inventions, (Ans. at 6),
and, as just discussed, the Examiner inferred that one goal of Grohoski’s
system was to minimize processor idle time in certain situations, (id. at 6).
Based on these findings, the Examiner found it would have been obvious to
make the proposed combination to improve overall system performance and
minimize processor idle time in specified contexts. (See id.) We agree with
these findings. To conclude otherwise, we would have to ignore common
sense and deprive one of skill in the art the creative inferences of an ordinary
person. That we cannot do. See KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398,
421 (2007) (“A person of ordinary skill is also a person of ordinary
creativity, not an automaton.”).
The Examiner bolstered this determination in the Answer by citing the
Supreme Court’s statement that “[t]he combination of familiar elements
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according to know methods is likely to be obvious when it does no more
than yield predictable results.” (Ans. at 20 (citing KSR, 550 U.S. 398).) The
Examiner also found it would have been obvious to try certain
modifications. (Id. at 21.) We need not consider whether the Examiner
made the factual findings necessary to support this additional reasoning
because the Examiner’s main rationale for combining the references—
improving overall system performance and minimizing processor idle
time—is sufficient to support the rejection.
Finally, Appellants have not persuaded us the proposed modifications
would change McDonald’s principle of operation. Appellants argue that if,
as proposed by the Examiner, the address 182 shown in Figure 3 above
originated from an instruction cache instead of a multiplexer, McDonald’s
system would no longer be able to avoid deadlock conditions. But
Appellants provide no supporting evidence or rationale for this assertion,
and it is unclear why changing the location the address originates from and
not the address itself would change how McDonald’s system functions.
Regardless, “it is not necessary that the inventions of the references be
physically combinable to render obvious the invention under review.” In re
Sneed, 710 F.2d 1544, 1550 (Fed. Cir. 1983).
DECISION
We have considered Appellants’ remaining arguments and found them
either waived, unpersuasive, or both. As the other rejected claims stand or
fall with the claims discussed above, we affirm the Examiner’s final
rejection of claims 1, 2, 4, 5, 9-11, and 17 under 35 U.S.C. § 103(a).
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No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1) (2011). See
37 C.F.R. § 1.136(a)(1)(iv).

AFFIRMED

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