Ex Parte Doany et alDownload PDFPatent Trial and Appeal BoardSep 6, 201613028814 (P.T.A.B. Sep. 6, 2016) Copy Citation UNITED STA TES p A TENT AND TRADEMARK OFFICE APPLICATION NO. FILING DATE 13/028,814 02/16/2011 49267 7590 09/08/2016 TUTUNJIAN & BITETTO, P.C. 401 Broadhollow Road, Suite 402 Melville, NY 11747 FIRST NAMED INVENTOR FUAD E. DOANY UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www .uspto.gov ATTORNEY DOCKET NO. YOR920100620US1 (163-385) CONFIRMATION NO. 9491 EXAMINER CHU, CHRIS H ART UNIT PAPER NUMBER 2874 NOTIFICATION DATE DELIVERY MODE 09/08/2016 ELECTRONIC Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the following e-mail address( es): patents@tb-iplaw.com PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE BEFORE THE PATENT TRIAL AND APPEAL BOARD Ex parte FUAD E. DOANY, BENJAMIN G. LEE, and CLINT L. SCHOW Appeal2015-003277 Application 13/028,814 Technology Center 2800 Before ADRIENE LEPIANE HANLON, CATHERINE Q. TIMM, and JAMES C. HOUSEL, Administrative Patent Judges. PERCURIAM. DECISION ON APPEAL 1 STATEMENT OF THE CASE Appellants2 filed an appeal under 35 U.S.C. § 134 from the Examiner's decision rejecting claims 1-25. We have jurisdiction under 35 U.S.C. §§ 6(b) and 134(a). We AFFIRM. 1 Our decision refers to the Specification filed Feb. 16, 2011 (Spec.), the Non-Final Office Action mailed Mar. 19, 2014 (Non-Final Act.), Appellants' Appeal Brief filed Aug. 11, 2014 (Br.), and the Examiner's Answer mailed Nov. 12, 2014 (Ans.). 2 Appellants identify the real party in interest as International Business Machines Corporation. Br. 3. Appeal2015-003277 Application I 3/028,8 I 4 The claims on appeal are directed to chip systems and methods for fabricating an optical signaling device (see, e.g., claims I, I3, and 23). The chip system includes a photonics chip and an electrical integrated circuit (IC) flip-chip coupled to the photonics chip to form an optochip (see, e.g., claim I). The IC and the photonics chip reside on the same side of a carrier. Id. Figure IA shows the chip system, and is reproduced below. 110 ,i ·104 ... r:.:--L·-· ,. ::::~ -. . ~ .... ~'''''''''''''''''''". "'''''''''''""'::* FIG. 1 A 116 Figure IA is a side view of an optical device. Figure IA depicts a platform IOO including an electrical integrated circuit (IC) I 04 coupled to a photonics chip I 02, such as via a flip-chip packaging process using solder I I5, to produce an optochip I IO that includes the electrical IC I 04 and the photonics chip I 02. Spec. i-fi-1 30, 33. The electrical IC I 04 and the photonics chip I 02 are then coupled to a chip 2 Appeal2015-003277 Application 13/028,814 carrier 106, such as via solder 117. Spec. iii! 30, 33. The chip carrier 106 includes a recess 112 to accommodate the photonics chip 102 and permit attachment of optical fibers 114 to an edge of the photonics chip. Spec. if 31. The chip carrier 106 may then be attached to a system board 116, such as via solder 118. Spec. if 33. Independent claim 1 is illustrative of the subject matter on appeal. Claim 1 is reproduced from the Claims Appendix of the Appeal Brief with limitations at issue in the appeal italicized: 1. A chip system, comprising: a photonics chip; and an electrical integrated circuit (IC) flip-chip coupled to the photonics chip to form an optochip, wherein one of the IC and the photonics chip includes an array of bond pads for attachment to the other of the IC and the photonics chip and the optochip having an array of bond pads for subsequent attachment to a carrier where the photonics chip includes an exposed edge to connect with at least one waveguide, wherein the IC and the photonics chip are disposed on a same side of the carrier. Br. 28 (Claims App'x) (emphasis added). The claims on appeal stand rejected as follows: (1) claims 1-3, 6, 7, 9, 10, 12-14, 17, 19, 20, and 22 under 35 U.S.C. § 102(b) as anticipated by Epitaux; 3 (2) claims 4, 8, 15, and 18 under 35 U.S.C. § 103(a) as unpatentable over Epitaux in view ofUrano;4 (3) claims 5 and 16 under 35 U.S.C. § 103(a) as being unpatentable 3 Epitaux, US 2008/0298818 Al, published Dec. 4, 2008 ("Epitaux"). 4 Urano et al., US 2009/0046456 Al, published Feb. 19, 2009 ("Urano"). 3 Appeal2015-003277 Application 13/028,814 over the combination of Epitaux in view of Hasegawa; 5 (4) claims 11 and 21under35 U.S.C. § 103(a) as being unpatentable over the combination of Epitaux in view of Block;6 and (5) claims 23-25 under 35 U.S.C. § 103(a) as being unpatentable over the combination of Epitaux in view of Dodson. 7 OPINION Rejection over Epitaux Claims 1-3, 6, 7, 9, 10, 12-14, 17, 19, 20, and 22 are rejected under 35 U.S.C. § 102(b) as anticipated by Epitaux. Appellants argue claims 1 and 13 as a group, and claims 3 and 17 as a separate group. Br. 9-15. We select claims 1 and 3 as representative of these groups. The remaining claims stand or fall with the claim from which they depend. Claim 1 The dispositive issue on appeal is whether Appellants have shown reversible error in the Examiner's finding that Epitaux discloses a photonics chip and a chip system in which an electrical integrated circuit and a photonics chip are disposed on a same side of a carrier, as recited in claim 1. The Examiner finds Epitaux discloses a chip system including a photonics chip and an electrical integrated circuit (IC), wherein the IC and the photonics chip are disposed on the same side of a carrier. Non-Final Act. 3. 5 Hasegawa et al., US 7,010,184 B2, issued Mar. 7, 2006 ("Hasegawa"). 6 Block et al., US 7,801,397 B2, issued Sept. 21, 2010 ("Block"). 7 Dodson et al., US 4,722,586, issued Feb. 2, 1988 ("Dodson"). 4 Appeal2015-003277 Application 13/028,814 The Examiner finds that the substrate 15, multi-port lens assembly 24, photodetectors 40, and laser diodes 42 together correspond to the claimed photonics chip. Ans. 2. To illustrate this, the Examiner provides an annotated copy of Figure 5 of Epitaux at page 3 of the Answer, which is reproduced below. Figure 5 depicts an exploded view of an optical transceiver embodiment. Figure 5 shows optical fibers 10 for connection to a multi-port lens assembly 24 (annotated in Figure 5 as element 24) that houses the photodetectors 40 and laser diodes 42, as well as collimating lenses 73 and focusing lenses 74. Epitaux i-fi-127, 34, 37, 39. As indicated in Figure 5, and explained in paragraph 35 of Epitaux, the multi-port lens assembly 24 is aligned with and fit within the substrate 15. 5 Appeal2015-003277 Application 13/028,814 Appellants contend Epitaux does not disclose a photonics chip. Br. 10-13. According to Appellants, "as discussed in paragraph [0027] of Epitaux, lenses must be mounted onto a substrate in Epitaux, and as such, Epitaux clearly does not employ a photonics chip in any way whatsoever." Appeal Br. 10. But Appellants do not provide any particular definition of "photonics chip" that would preclude the structure identified by the Examiner (Epitaux's lens assembly 24, photodetectors 40, laser diodes 42, mounted on substrate 15) as meeting the requirements of a "photonics chip." Appellants state that "one of ordinary skill in the art would know that a photonics chip converts light to electric, and vice versa" and Epitaux is merely a waveguide and element 15 is simply a substrate. Br. 12. But as found by the Examiner, Epitaux's mounted optical components function as argued by Appellants. Ans. 3--4. Epitaux's assembly includes photodetectors that covert light to electricity and laser diodes that convert electricity to light. Epitaux i-f 28. Further, Epitaux discloses that its transceiver "functions to convert optical signals arriving on optical fibers 10 to electrical signals" and "electrical signals provided to the contacts are converted to optical signals and provided on the optical fibers 10." Epitaux ,-r 26. Appellants contend one of ordinary skill in the art would also know that a photonics chip includes built-in optical components and the chip (substrate 15) ofEpitaux is used only in a structural role. Br. 12-13. Appellants do not cite any evidence in support of this argument. The Examiner further finds Appellants have not defined a "photonics chip" in the Specification. Ans. 3. We agree there is no definition in the Specification of "photonics chip" that excludes the substrate-mounted 6 Appeal2015-003277 Application 13/028,814 optical components taught by Epitaux. Turning to the Specification, what we find is a discussion of what types of optical devices may be included in a photonics chip. The Specification states: The photonics chip 102 may include active and/ or passive optical devices, including but not limited to lasers, optical modulators, photodetectors, waveguides, wave division multiplexing (WDM) multiplexers and demultiplexers, power splitters, input/output couplers, mode converters, switches, detectors, spot-size converters, grating couplers, etc. Spec. ,-r 34. In places, Appellants' Specification refers to "integrated photonics chips" and photonic circuits that "offer extremely high-density integration." Spec. i-fi-1 4, 22, 29 (emphasis added). But the Specification does not clearly limit a "photonics chip" to an integrated photonics chip. According to the Specification, a photonic chip "may be fabricated in silicon or other semiconductor material." Spec. i130. But further according to the Specification: The present approach is applicable to other optical component technologies such as: InP; GaAs photonic integrated circuits; other III-V or II-VI semiconductors used to construct optical devices; polymer-based photonic devices; etc. Spec. i-f 30. A photonic chip may, for instance, be a "polymer-based photonic device." Id. Appellants do not limit claim 30 to an integrated photonics chip. During prosecution before the Examiner, the claim language should be given its broadest reasonable meaning of the words in their ordinary 7 Appeal2015-003277 Application 13/028,814 usage as they would be understood by one of ordinary skill in the art, taking into account any definitions or enlightenment contained in the written description of Appellants' Specification. See In re Morris, 127 F.3d 1048, 1054 (Fed. Cir. 1997). The Examiner defines "photonics chip" as "merely a substrate having photonics capabilities," and, absent any evidence to the contrary, we determine that the Examiner's definition is consistent with how one of ordinary skill in the art would read the Specification. Ans. 4. Appellants have not provided evidence to refute that interpretation. The Examiner finds Epitaux's assembly, which includes a multi-port lens assembly 24 (including photodetectors 40, and laser diodes 42) mounted on substrate 15, is a photonic chip within the meaning of claim 1. Ans. 3. Appellants have not demonstrated a reversible error in this finding. In addition, Appellants argue Epitaux does not disclose that an IC and a photonics chip are disposed on a same side of a carrier, as recited in claim 1. Br. 10-12. But Appellants do not address the Examiner's actual finding with any specificity. Appellants argue that substrate 15 is not the carrier required by the claim, but the Examiner finds the socket 25 of Epitaux is the required carrier, not substrate 15. Compare Br. 11-12 with Ans. 4. The Examiner finds Figure 3 of Epitaux depicts the transceiver 12 mounted to the socket 25. Ans. 4. Epitaux discloses that the transceiver 12 includes the substrate 15 and the multi-port lens assembly 24, which is connected to optical fibers 10. Epitaux i-f 27. The Examiner finds the transceiver 12 is on top of the socket 25 (which functions as a carrier) and the IC 31 is on top of the photonics chip. Ans. 4. In view of this, the 8 Appeal2015-003277 Application 13/028,814 Examiner finds the IC 31 and photonics chip of Epitaux are disposed on a same side of the socket 25, as recited in claim 1. Ans. 4. Figure 3 ofEpitaux depicts the transceiver 12, which includes the multi-port lens assembly 24, as being mounted to the socket 25 and Figure 5 depicts the IC 31 being mounted to a top side of the photonics chip (the combination of the substrate 15, multi-port lens assembly 24, photodetectors 40, and laser diodes 42). Therefore, the disclosure of Epitaux supports the Examiner's findings and Appellants' arguments, which focus on the substrate 15 as the carrier, do not address the Examiner's rejection. Therefore, for the reasons discussed above and those set forth in the Examiner's Answer, we sustain the Examiner's§ 102(b) rejection of claims 1, 2, 6, 7, 9, 10, 12-14, 19, 20, and 22 over Epitaux. Claims 3 and 17 Claim 3 depends from claim 1 and further recites "wherein the carrier includes a recess in a top surface configured to receive the photonics chip." Claim 17 depends from claim 13 and further recites "wherein the recess [of the carrier] is configured to receive one of the IC and the photonics chip." The Examiner finds the carrier of Epitaux includes a recess in its top surface and is configured to receive the photonics chip, citing Figures 3 and 4 of Epitaux. Non-Final Act. 3. Appellants contend Figures 3 and 4 of Epitaux do not disclose a carrier with a recess configured to receive a chip of any kind but only disclose a connection between socket 25 and an optical transceiver. Br. 14-- 15. 9 Appeal2015-003277 Application 13/028,814 As found by the Examiner, Figure 3 of Epitaux shows a socket 25, which functions as a carrier, as having raised portions at its periphery and rubber bumps 20, used to make a connection to a transceiver 12, located within a recess formed by the raised portions. Ans. 5. As further found by the Examiner, Figure 4 of Epitaux depicts a socket 27 having a central portion recessed within a raised peripheral edge portion. Ans. 5. Thus, Appellants' argument does not demonstrate a reversible error in the Examiner's findings. For the reasons discussed above and those set forth in the Examiner's Answer, we sustain the Examiner's § 102(b) rejection of claims 3 and 17 over Epitaux. Rejection over Epitaux and Urano Claims 4, 8, 15, and 18 are rejected under 35 U.S.C. § 103(a) as unpatentable over Epitaux in view of Urano. We select claim 4 as representative for discussing the issues on appeal. The dispositive issue on appeal is whether Appellants have shown it would not have been obvious to modify Epitaux in view of Urano because Urano is non-analogous art. The Examiner finds Epitaux does not disclose a recess of a carrier that permits more than one chip therein, as recited in claim 4. Non-Final Act. 5. The Examiner finds Urano discloses a plurality of light emitting diode (LED) chips received in a single recess of a carrier. Non-Final Act. 5. The Examiner concludes it would have been obvious to mount multiple components in a recess in the transceiver of Epitaux so multiple transceivers can be connected at once. Non-Final Act. 5. 10 Appeal2015-003277 Application 13/028,814 Appellants assert one of ordinary skill in the art would have known that a light apparatus using LED lights, as disclosed by Urano, is completely unrelated to a system including a photonics chip and a cylindrical lighting fixture with an opening at the bottom is not equivalent to a recess in a substrate configured to receive a photonics chip. Br. 17-18. Thus, Appellants appear to be arguing that it would not have been obvious to modify Epitaux in view of Urano because Urano is non-analogous art. But the question is not whether LED lighting systems are related or "completely unrelated" to systems including photonic chips; it is whether one of ordinary skill in the art would have looked to other carriers in other electronic systems to solve problems or make design changes to the carrier of Epitaux's optical transceiver when faced with the problem of including multiple transceivers. As found by the Examiner, Epitaux already teaches a carrier (socket 25) having a recess for supporting a transceiver that includes a photonics chip. Ans. 5. As further found by the Examiner, Urano also has a carrier 90 for carrying optical devices (the LED chip units 1). Ans. 5; Urano i-f 48; Fig. 1. Both the field of endeavor and problems to be addressed are sufficiently close to find that Urano is the type of analogous art that those of ordinary skill in the art would have consulted. Under the conventional non-analogous art test [t]wo criteria have evolved for determining whether prior art is analogous: (1) whether the art is from the same field of endeavor, regardless of the problem addressed, and (2) if the reference is not within the field of the inventor's endeavor, whether the reference still is reasonably pertinent to the particular problem with which the inventor is involved. 11 Appeal2015-003277 Application 13/028,814 Jn re Clay, 966 F.2d 656, 658-59 (Fed. Cir. 1992); Jn re Wood, 599 F.2d 1032, 1036 (CCPA 1979). Furthermore, "[t]he Supreme Court's decision in KSR International Co. v. Teleflex, Inc., 550 U.S. 398 ... (2007), directs us to construe the scope of analogous art broadly." Wyers v. Master Lock Co., 616 F.3d 1231, 1238 (Fed. Cir. 2010). We must take care not to adhere to rigid and mandatory formulas that overly limit the inquiry. KSR Int 'l Co. v. Teleflex Inc., 550 U.S. 398, 419 (2007). In view of the above, Appellants' arguments do not persuade us that the Examiner reversibly erred. Appellants do not argue claims 5, 15, and 18 separately from claim 4. Br. 18-19. Therefore, for the reasons discussed above and those set forth in the Examiner's Answer, we sustain the Examiner's§ 103(a) rejection of claims 4, 8, 15, and 18 over the combination of Epitaux and Urano. Rejection over Epitaux and Hasegawa Claims 5 and 16 are rejected under 35 U.S.C. § 103(a) as being unpatentable over the combination of Epitaux in view of Hasegawa. We select claim 5 as representative for deciding the issues on appeal. Claim 5 depends from claim 3, which depends from claim 1, and further recites "wherein the recess permits exposure of a plurality of edges of the photonics chip to permit access for optical inputs and outputs." In the rejection of claims 5 and 16, the Examiner finds Epitaux discloses a recess permitting exposure for a plurality of edges, citing Figure 3 of Epitaux, but does not disclose permitting access to further optical inputs and outputs. Non-Final Act. 5. The Examiner finds Hasegawa discloses a photonics chip having a plurality of exposed edges for optical inputs and 12 Appeal2015-003277 Application 13/028,814 outputs, citing the planar lightwave circuit chip 1 depicted in Figure 1 of Hasegawa. Non-Final Act. 6. The Examiner concludes it would have been obvious to mount multiple inputs and outputs to the transceiver module of Epitaux to allow more connections and increase the density of the device. Non-Final Act. 6. Appellants argue Hasegawa does not disclose a recess of any kind or a recess that permits exposure of a plurality of edges of a photonics chip to permit access for optical inputs and outputs. Br. 20. But this argument does not address the Examiner's rejection, which does not rely upon Hasegawa as teaching a recess. The Examiner finds Epitaux discloses a recess. Specifically, the Examiner finds the carrier 25 depicted in Figure 3 of Epitaux has a recess that permits exposure to a plurality of edges of a transceiver 12. Appellants' arguments do not demonstrate a reversible error in the Examiner's findings. For the reasons discussed above and those set forth in the Examiner's Answer, we sustain the Examiner's§ 103(a) rejection of claims 5 and 16 over the combination of Epitaux and Hasegawa. Rejection over Epitaux and Block Claims 11 and 21 are rejected under 35 U.S.C. § 103(a) as being unpatentable over the combination of Epitaux in view of Block. For claims 11 and 21, Appellants merely reiterate the arguments set forth in support of the patentability of claim 1 and contend Block does not remedy the deficiencies of the references applied in the rejection of claim 1. 13 Appeal2015-003277 Application 13/028,814 Br. 21-23. For the reasons set forth above, there are no deficiencies in the rejection of claim 1 that require curing by Block. Therefore, for the reasons discussed above and those set forth in the Examiner's Answer, we sustain the Examiner's § 103(a) rejection of claims 11 and 21 over the combination of Epitaux and Block. Rejection over Epitaux and Dodson Claims 23-25 are rejected under 35 U.S.C. § 103(a) as being unpatentable over the combination of Epitaux in view of Dodson. We select claim 23 as representative of the issues on appeal. For the rejection of claims 23-25, Appellants state the Examiner finds Epitaux does not disclose flip-chip bonding using a first solder and a second solder having a lower melting point than the first solder, as recited in claim 23. Br. 23. Appellants argue the Examiner relies upon U.S. 4,722,856 to disclose such solder but argues U.S. 4,722,856 is directed to methods for depositing monomolecular layers on a substrate and does not list Dodson as an inventor. Br. 23-24. In view of this, Appellants assert Dodson does not disclose first and second solders of claim 23 and therefore does not cure the deficiencies of Epitaux. Br. 24-25. As stated by the Examiner on page 6 of the Answer, Dodson was correctly cited as U.S. 4,722,586 in the Non-Final Office Action mailed March 19, 2014. Therefore, Dodson was correctly cited in the Office Action that preceded Appellants' Appeal Brief, which was filed on filed August 11, 2014. As a result, Appellants have not directed to any error in the Examiner's§ 103 rejection over Epitaux and Dodson. 14 Appeal2015-003277 Application 13/028,814 Appellants further argue claim 23 includes similar limitations to claim 1 but Dodson does not cure the deficiencies of Epitaux discussed above with regard to the rejection of claim 1. Br. 25. For the reasons set forth above, there are no deficiencies in the rejection of claim 1 that require curing by Dodson. Appellants do not argue claims 24 and 25 separately from claim 23. Br. 25-26. Therefore, for the reasons discussed above and those set forth in the Examiner's Answer, we sustain the Examiner's § 103(a) rejection of claims 23-25 over the combination of Epitaux and Dodson. DECISION The decision of the Examiner rejecting claims 1-25 under 35 U.S.C. §§ 102(b) and 103(a) is affirmed. No time period for taking any subsequent action in connection with this appeal may be extended under 37 C.F.R. § 1.136(a)(l). AFFIRMED 15 Copy with citationCopy as parenthetical citation