Ex Parte Do et al

Patent Trial and Appeal Board

Dec 19, 2014

11307317 (P.T.A.B. Dec. 19, 2014)

UNITED STATES PATENT AND TRADEMARK OFFICE
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BEFORE THE PATENT TRIAL AND APPEAL BOARD
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Ex parte BYUNG TAI DO and SUNG UK YANG

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Appeal 2012-010823
Application 11/307,317
Technology Center 2800
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Before CHUNG K. PAK, TERRY J. OWENS, and RICHARD M.
LEBOVITZ, Administrative Patent Judges.

LEBOVITZ, Administrative Patent Judge.

DECISION ON APPEAL
This appeal involves claims to an integrated circuit system. The
Examiner has rejected the claims as indefinite under 35 U.S.C. § 112 and as
obvious under 35 U.S.C. § 103(a). We have jurisdiction under 35 U.S.C.
§ 6(b). The Examiner is affirmed but the affirmance is designated as a new
ground of rejection.
STATEMENT OF THE CASE
Appellants appeal from the Examiner’s final rejection of claims 11,
12, 14–16, 19, and 20. Appeal Br. 5. The claims stand rejected by the
Examiner as follows:
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1. Claims 11, 12, 14–16, 19, and 20 under 35 U.S.C. § 112, second
paragraph (pre-AIA), as indefinite for failing to particularly point out and
distinctly claim the subject matter which applicant regards as the invention.
Answer 4.
2. Claims 11, 12, 14–16, 19, and 20 under 35 U.S.C. § 103(a) (pre-
AIA) as obvious in view of Kurita.1 Answer 5.
Claim 11 is representative and reads as follows:
11. An integrated circuit system comprising:
a substrate;
an integrated circuit attached to the substrate; and
a waferscale spacer system on the integrated circuit, a
portion of the waferscale spacer system having feature sizes of
fabricated circuitry on a singulated wafer.

SECTION 112 REJECTION
The Examiner found claim 11 indefinite because “one of ordinary
skill in the art could not ascertain the metes and bounds” of the claimed
limitation “the waferscale spacer system having feature sizes of fabricated
circuitry on a singulated wafer.” Answer 4. The Examiner complained that
the sizes of the fabricated circuitry could change, that the “feature sizes are
not defined in the Specification,” 2 and it was not clear what components of
fabricated circuitry are covered by the claims. Id. at 4–5. The Examiner
also found the recited “portion of the waferscale system” to be indefinite
because it is not clear what part of the waferscale spacer system is
referenced. Id. at 6.

1 Kurita et al., US 6,930,396 B2, issued Aug. 16, 2005.
2 The “Specification” is Application No. 11/307,317 which hereinafter is
referred to as the ’317 Application.
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With respect to the lack of a definition of “feature sizes,” Appellants
point to paragraphs 68 and 72 of the ’317 Application. Appeal Br. 9–10;
Reply Br. 4. Paragraph 68 does not mention feature size, although it refers
to the height of the waferscale spacer, but height is not recited in claim 11.
Paragraph 72 describes features sizes as being “used to manufacture
waferscale spacer patterns and dimensions unachieved by existing methods.”
The paragraph also contains the following disclosure:
[T]he semiconductor process and features may be process steps,
such as resist application and etching, and feature sizes, such as
line widths, heights, and other dimensions, used to fabricate
circuitry on the wafer. Stacking of chips with varying die sizes
requires a spacer between the die when the top die is either the
same size or larger than the bottom to avoid damage to its
wires.
It is not clear from this passage whether the waferscale spacer must
have all the dimensions of the fabricated circuitry, or whether the claim
limitation would be met if a waferscale spacer had one dimension of the
circuitry, but not other dimensions. Moreover, as the Examiner pointed out,
the circuit comprises different components and it is not clear whether the
claim limitation is met when dimensions of only one circuit component is
met, or whether the dimensions must having feature sizes of all the
components of the fabricated circuitry.
Appellants contend that they have the right to be their own
“lexicographer.” Appeal Br. 10.
Although an inventor is indeed free to define the specific terms
used to describe his or her invention, this must be done with
reasonable clarity, deliberateness, and precision. “Where an
inventor chooses to be his own lexicographer and to give terms
uncommon meanings, he must set out his uncommon definition
in some manner within the patent disclosure” so as to give one
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of ordinary skill in the art notice of the change. See Intellicall,
Inc., v. Phonometrics, Inc., 952 F.2d 1384, 1387-88 (Fed. Cir.
1992).
In re Paulsen, 30 F.3d 1475, 1480 (Fed. Cir. 1994).
The ’317 Application did not set forth a definition of “feature
sizes” with the requisite clarity, deliberateness, and precision.
In sum, Appellants’ response to the rejection did not adequately
address the Examiner’s finding that “feature sizes” is indefinite.
The claim also contains the limitation that “a portion of the waferscale
spacer system having feature sizes of fabricated circuitry.” The Examiner
determined that “a portion of” is indefinite because it cannot be ascertained
whether the portion is a part of spacer, a single spacer, or a part of a pattern
of spacers. Appellants identified support for the limitation in paragraph 30
of the ’317 Application. Appeal Br. 7. However, this paragraph only
identifies element 102 as the complete waferscale spacer system, and does
not clarify what constitutes a “portion” of it. As Appellant did not clarify
the meaning of “portion of,” and it is not clear from the claim or ’317
Application what part of the waferscale system represents “a portion” of it,
we agree that the term is indefinite.
For the foregoing reasons, we affirm the Examiner’s rejection of
claim 11, and dependent claims 12, 14–16, 19, and 20, as indefinite.

OBVIOUSNESS
Claim 11 is directed to an integrated circuit system comprising a
substrate, an integrated circuit, and a waferscale spacer system. The
Examiner found that Kurita disclosed all the elements of the claim, but not
the recited limitation of “a portion of the waferscale spacer system having
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feature sizes of fabricated circuitry on a singulated wafer.” Answer 6. For
this rejection, we will consider a “portion” to be a single spacer, and the
dimension to be at least height.
The Examiner found that it would have been obvious to one of
ordinary skill in the art “to use a spacer pattern (features or height or state of
matter) having feature sizes of fabricated circuitry on a singulated wafer.”
Answer 6. The Examiner also stated that “the determination of the optimum
size of the features would be within the skill of one of ordinary skill in the
art, for its benefit in optimizing the performa[n]ce of the integrated circuit.”
Id. Furthermore, the Examiner found that “size of the waferscale system
would determine the amount of support, stability and strength provided to
the device, and would be prima facie obvious to one of ordinary skill in the
art.” Id. at 11. The Examiner noted that “changes in size do not constitute a
patentable difference.” Id. at 6.
Appellants contend that the Examiner “has not provided a basis for
the rejection of claim 11, but merely provides a conclusory statement
without support.” Appeal Br. 16; Reply Br. 7. Furthermore, Appellants
reject the Examiner’s statement that a change in size is not patentable;
rather, Appellants’ argue they are claiming matching feature size of the
spacers to the feature size of the circuitry, a relationship which Appellants
contend is not described in Kurita, i.e., decreasing the spacer size as the
circuitry decreases. Appeal Br. 17 and 19.
We agree with Appellants that the Examiner’s reasoning for
“optimizing” the waferscale of Kurita to have a feature size of the fabricated
circuitry is conclusory. For example, the Examiner did not explain why
matching feature size to the circuitry would optimize performance and
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provide the necessary “support, stability and strength.” Furthermore, the
Examiner did not establish that the difference between the claimed invention
and Kurito was a simply change in size because, as acknowledged by the
Examiner, the dimensions of the spacer system are not disclosed by Kurito.
Nonetheless, the ’317 Application admits that it was an art-recognized
goal to decrease the size of integrated circuit packages. ’317 Application
¶¶ 2–7. See also Answer 5: 2–4. Thus, the skilled worker would have had
reason to shrink the feature size of a spacer as the circuitry was made
smaller in order to reduce the size of the integrated circuit package. The
skilled worker would have had reason to make the feature size, particularly
the height of the spacer, comparable to the feature size of the circuitry in
order to stack as many circuits together as possible in the least amount of
space.
Since our reasoning differs from the Examiner’s, we shall designate
this as a new ground of rejection under 37 C.F.R. § 41.50(b). When the
Board designates a new ground of rejection under 37 C.F.R. § 41.50(b), the
appellant, as to each claim so rejected, has the option of:
(A) reopening prosecution before the examiner by submitting an
appropriate amendment and/or new evidence (37 C.F.R. § 41.50(b)(1)); or
(B) requesting rehearing before the Board (37 C.F.R. § 41.50(b)(2)).
The amendment and/or new evidence under 37 C.F.R. § 41.50(b (1),
or the request for rehearing under 37 C.F.R. § 41.50(b)(2), must be filed
within 2 months from the date of the Board’s decision. In accordance with
37 C.F.R. § 41.50(f), this 2-month time period may not be extended by the
filing of a petition and fee under 37 C.F.R. § 1.136(a), but only under the
provisions of 37 C.F.R. § 1.136(b),

AFFIRMED

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