Ex Parte Do et alDownload PDFPatent Trial and Appeal BoardDec 27, 201613430577 (P.T.A.B. Dec. 27, 2016) Copy Citation United States Patent and Trademark Office UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O.Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 13/430,577 03/26/2012 Byung Tai Do 2515.0143 DIV 9314 112165 7590 12/29/2016 STATS ChipPAC/PATENT LAW GROUP: Atkins and Associates, P.C. 55 N. Arizona Place, Suite 104 Chandler, AZ 85225 EXAMINER GRAYBILL, DAVID E ART UNIT PAPER NUMBER 2894 NOTIFICATION DATE DELIVERY MODE 12/29/2016 ELECTRONIC Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the following e-mail address(es): main@plgaz.com PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE BEFORE THE PATENT TRIAL AND APPEAL BOARD Ex parte BYUNG TAI DO, REZA A. PAGAILA, and LINDA PEI EE CHUA Appeal 2015-008121 Application 13/430,577 Technology Center 2800 Before BEVERLY A. FRANKLIN, MICHAEL P. COLAIANNI, and N. WHITNEY WILSON, Administrative Patent Judges. FRANKLIN, Administrative Patent Judge. DECISION ON APPEAL Appellants request our review under 35 U.S.C. § 134 of the Examiner’s decision rejecting claims 1—7, 9—15, 17—26, 29, 30, 33, 34, and 36—38. We have jurisdiction over the appeal under 35 U.S.C. § 6(b). Appeal 2015-008121 Application 13/430,577 STATEMENT OF THE CASE Claim 1 is illustrative of Appellants’ subject matter on appeal and is set forth below: 1. A semiconductor device, comprising: a semiconductor wafer including a plurality of semiconductor die and a recessed region around the semiconductor die; a first bumpformed over the semiconductor die; a second bump formed in the recessed region of the semiconductor wafer; a bond wire formed between the first bump and second bump; a third bump formed over the bond wire and first bump; and an encapsulant deposited over the semiconductor wafer and third bump. The Examiner relies on the following prior art references as evidence of unpatentability: Lua Meguro Lam US 2008/0157360 US 2009/0020890 A1 US 8,018,065 B2 Jul. 3, 2008 Jan. 22, 2009 Sept. 13,2011 2 Appeal 2015-008121 Application 13/430,577 THE REJECTIONS 1. Claims \-A, 6, 7, 9-15, 17-20, 26, 29, 30, 33, 34, 37 and 38 stand rejected under pre-AIA 35 U.S.C. § 103(a) as being unpatentable over Meguro and Lua. 2. Claim 5 is rejected under pre-AIA 35 U.S.C. § 103(a) as being unpatentable over Meguro and Lua as applied to claim 1, and further in view of Lam. 3. Claim 36 is rejected under pre-AIA 35 U.S.C. § 103(a) as being unpatentable over Meguro and Lua as applied to claim 30, and further in combination with Lam. 4. Claims 21—25 stand rejected under pre-AIA 35 U.S.C. § 103(a) as being unpatentable over Meguro, Lua, in view of Lam. ANALYSIS We group the claims (as identified hereafter), and consider the respective groupings, based upon Appellants’ presented arguments. 37 C.L.R. § 41.37(c) (l)(iv)(2014). We review the appealed rejections for error based upon the issues identified by Appellants and in light of the arguments and evidence produced in the record. Cf. Ex parte Frye, 94 USPQ2d 1072, 1075 (BPAI 2010) (precedential) (cited with approval in In re Jung, 637 L.3d 1356, 1365 (Led. Cir. 2011) (“it has long been the Board’s practice to require an 3 Appeal 2015-008121 Application 13/430,577 applicant to identify the alleged error in the examiner’s rejections”)). After having considered the evidence presented in this Appeal and each of Appellants’ contentions (found the Appeal Brief and as reiterated in the Reply Brief1), we are not persuaded that Appellants identify reversible error, and we affirm the Examiner’s rejections for substantially the reasons expressed in the Final Office Action and in the Answer. We add the following primarily for emphasis. Rejections 1,2, and 3 Claims 1, 2—6 and 262 Appellants argue that Meguro teaches away from the use of stud bumps because stacking stud bumps increases manufacturing work and cost, and refer to paragraph [0006] of Meguro. Appeal Br. 8—9. Appellants argue that therefore Meguro teaches away from applying Lua as proposed in the rejection. Id. We agree with the Examiner that such arguments are unpersuasive. Ans. 15—18. We add that it is well settled that merely because “[a] combination would not be made by businessmen for economic 1 With regard to newly presented arguments set for in the Reply Brief (for example, arguments pertaining to claims 14, 21, and 30 (pp. 8—10)), we decline to consider any new argument when not accompanied by a showing of good cause explaining why the argument could not have been presented in the Appeal Brief. See Ex parte Borden, 93 USPQ2d 1473, 1477 (BPAI 2010) (informative). 2 Appellants include claim 5 in this grouping of claims. Rejection 2 involves an obviousness rejection of claim 5 over Meguro and Lua in view of Lam. 4 Appeal 2015-008121 Application 13/430,577 reasons does not mean that persons skilled in the art would not make the combination.” In re Farrenkopf 713 F.2d 714, 718 (Fed. Cir. 1983). Appellants also argue that Lua does not contain a motivation to combine his invention with Meguro for the reasons stated on pages 9—12 of the Appeal Brief, the reasons again involving associated costs. However, as stated supra, “[a] combination would not be made by businessmen for economic reasons does not mean that persons skilled in the art would not make the combination. Id. Appellants also submit that the Examiner does not provide sufficient motivation for the proposed modification of Meguro. Appeal Br. 11. However, we agree with the Examiner’s stated reply made on pages 19—20 of the Answer, and are unpersuaded but such argument. Finally, Appellants argue that neither Meguro nor Lua suggests an encapsulant deposited over the die and third bump. Appeal Br. 13. However, on page 8 of the Final Office Action, the Examiner correctly found that Lua teaches an encapuslant (a dielectric layer) deposited over the semiconductor wafer 40 and bump 100 wherein the bump 100 is exposed through the encapuslant. Lua, para. [0059]. The Examiner reiterates this finding in reply to Appellants’ argument. Ans. 24. We are thus unpersuaded by such argument. In view of the above, we affirm the rejection of claims 1, 2—6 and 26. Claims 7, 9-13, 37, and 38 Appellants rely upon similar arguments as presented for claims 1, 2—6 and 26 (of Rejection 1). Appeal Br. 13—18. Hence, we also affirm the rejection of these claims for similar reasons. 5 Appeal 2015-008121 Application 13/430,577 Claims 14, 15, 17—20, and 29 Appellants rely upon similar arguments as presented for claims 1, 2—6 and 26. Appeal Br. 18—24. Hence, we also affirm the rejection of these claims for similar reasons. Claims 30, 33, 34, and 36- Appellants rely upon similar arguments as presented for claims 1, 2—6 and 26. Appeal Br. 30—35. Hence, we also affirm the rejection of these claims for similar reasons. Rejection 4 Appellants rely upon similar arguments for Rejection 4 as presented for the other rejections. Appeal Br. 24—30. We therefore affirm Rejection 4 for similar reasons. DECISION Rejections 1, 2, 3, and 4 are affirmed. 3 Claim 36 is rejected in Rejection 3. Appellants group this claim with claims 30, 33, 34, and 36. 6 Appeal 2015-008121 Application 13/430,577 TIME PERIOD No time period for taking any subsequent action in connection with this appeal may be extended under 37 C.F.R. § 1.136(a). See 37 C.F.R. § 1.136(a). ORDER AFFIRMED 7 Copy with citationCopy as parenthetical citation