Ex Parte Disney

Board of Patent Appeals and Interferences

Feb 25, 2010

10929590 (B.P.A.I. Feb. 25, 2010)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________

Ex parte DONALD RAY DISNEY
____________

Appeal 2008-005465
Application 10/929,590
Technology Center 3600
____________

Decided: February 25, 2010
____________

Before KENNETH W. HAIRSTON, JOSEPH F. RUGGIERO, and
ROBERT E. NAPPI, Administrative Patent Judges.
HAIRSTON, Administrative Patent Judge.

DECISION ON APPEAL
Appellant appeals under 35 U.S.C. § 134 from a final rejection of
claims 36 to 38 and 40 to 50. We have jurisdiction under 35 U.S.C. § 6(b).
We will reverse the anticipation rejection of claims 36, 40 to 42, 45,
and 47, and reverse the obviousness rejections of claims 37, 38, 46, and 48
to 50. We will sustain the obviousness rejection of claims 43 and 44.
Appeal 2008-005465
Application 10/929,590

2
Appellant has invented a vertical high-voltage transistor formed in a
pair of first trenches that define a mesa in a substrate of a first conductivity
type. A field plate is disposed in each of the first trenches, and the field
plate is separated from the mesa by a dielectric layer. A second trench is
formed in the dielectric, and an insulated gate is disposed in the second
trench between the mesa and the field plate (Figs. 5A-5K; Spec. 1, 3, 5 to 9,
and 13-20; Abstract).
Claims 36 and 43 are illustrative of the claimed invention, and they
read as follows:
36. A vertical high-voltage transistor comprising:
a substrate of a first conductivity type;
a pair of first trenches in the substrate that define a mesa;
a field plate disposed in each first trench of the pair of first trenches,
the field plate being separated from the mesa by a dielectric layer;
a second trench in the dielectric layer;
an insulated gate disposed in the second trench between the mesa and
the plate member.
43. A vertical high-voltage transistor comprising:
first and second trenches that define a mesa having first and second
sidewalls in a semiconductor substrate, the first and second being filled with
a dielectric material that covers the first and second sidewalls;
first and second field plates disposed in the dielectric material of the
first and second trenches, respectively, the first and second field plates
having a first vertical depth and being respectively insulated from the first
Appeal 2008-005465
Application 10/929,590

3
and second sidewalls of the mesa in a lateral direction, and insulated from
the semiconductor substrate in a vertical direction, by the dielectric material;
first and second gate members disposed in the dielectric material
between the first and second sidewalls of the mesa, and the first and second
field plates, respectively, the first and second gate members having a second
vertical depth that is less than 20% of the first vertical depth.
The prior art relied upon by the Examiner in rejecting the claims on
appeal is:
Lee US 5,122,848 June 16, 1992
Baliga US 5,998,833 Dec. 7, 1999
Fujishima US 6,316,807 B1 Nov. 13, 2001
(filed Dec. 31, 1998)
Baliga US 6,525,372 B2 Feb. 25, 2003
(filed Nov. 16, 2000)
Wolf, Silicon Processing for the VLSI Era, Volume 3: The Submicron
MOSFET, Lattice Press, 1995, pp. 136-37.
Merriam-Webster’s Collegiate Dictionary, Tenth Edition, Merriam-Webster,
Inc., p. 1259.
The Examiner rejected claims 36, 40 to 42, 45, and 47 under 35
U.S.C. § 102(e) based upon the teachings of Fujishima.
The Examiner rejected claims 37 and 38 under 35 U.S.C. § 103(a)
based upon the teachings of Fujishima and Lee.
The Examiner rejected claims 43 and 44 under 35 U.S.C. § 103(a)
based upon the teachings of Baliga ‘372.
The Examiner rejected claims 46 and 48 to 50 under 35 U.S.C.
§ 103(a) based upon the teachings of Fujishima and Baliga ‘833.
Appeal 2008-005465
Application 10/929,590

4
Anticipation
With respect to claims 36, 40 to 42, 45, and 47, Appellant argues inter
alia (App. Br. 15-17) that plug 61 in Fujishima is not a field plate, and is
merely an interconnect that provides electrical connection to drain electrode
52.
Obviousness
With respect to claims 37 and 38, Appellant argues (App. Br. 17, 18)
that neither Fujishima nor Lee describes a field plate disposed in a trench as
set forth in the claims. With respect to claims 43 and 44, Appellant argues
(App. Br. 19-22) that the Rule 131 declaration evidence is sufficient to
remove the Baliga ‘372 reference from consideration as prior art. With
respect to claims 46, and 48 to 50, Appellant argues (App. Br. 24) that
neither Fujishima nor Baliga ‘833 teaches the noted field plate.

ISSUES
Anticipation
Has Appellant demonstrated that the Examiner erred by finding that
plug 61 in Fujishima is a field plate?
Obviousness
Has Appellant demonstrated that the Examiner erred by finding that
the applied references to Fujishima and Lee describe a field plate disposed in
a trench as required by claims 37 and 38?
Has Appellant demonstrated that the Examiner erred by finding that
the Rule 131 declaration is insufficient to remove the Baliga ‘372 reference
from consideration as prior art in the rejection of claims 43 and 44?
Appeal 2008-005465
Application 10/929,590

5
Has Appellant demonstrated that the Examiner erred by finding that
the applied references to Fujishima and Baliga ‘833 teach a field plate as set
forth in claims 46, and 48 to 50?

FINDINGS OF FACT (FF)
1. Fujishima describes a Trench Lateral Power MISFET in which a
drain electrode 52 at the surface of the MISFET is connected to a drain
region 58 in the bottom of the trench via a polysilicon plug 61 (Fig. 5; col. 1,
1l. 14, 15; col. 2, ll. 28 to 67; col. 6, ll. 18 to 46; col. 7, ll. 51 to 57).
2. Lee describes an insulated-gate vertical FET in which the substrate
material can be either P-type or N-type silicon formed in a wafer, epitaxial
layer, or well (Fig. 8; col. 2, ll. 27 to 31).
3. Appellant has not challenged the Examiner’s findings (Final Rej. 8,
9) that Baliga ‘372 describes all of the vertical high-voltage transistor
structure set forth in claims 43 and 44.
4. The Rule 131 declaration submitted by the inventor seeks to
establish invention prior to the November 16, 2000 filing date for Baliga
‘372. The declarant/inventor’s laboratory notebook has an entry dated June
9, 2000 that lists thickness as well as height values for draft pillars (Exhibit
1, A-12). Several pages later in the same declaration, carrier solution values
are provided for the drift region length, the drift region thickness, and the
dielectric region thickness (Exhibit 1, A-15). The next page of the
declaration illustrates a gate poly and a field plate poly, and the following
explanation of “Added Vertical (trench) Gate 3µm Long; with Pbody 2.5 µm
long, N+ Source 0.2 µm long” (Exhibit 1, A-16). The declarant/inventor’s
Appeal 2008-005465
Application 10/929,590

6
laboratory notebook has an entry dated April 30, 2001 that describes a
MEDICI modeling simulation program results that had a Lgate value of 3.0,
a Ldrift value of 50, and a Tbox value of 3.0 (Exhibit 4, A-36, A-37).
5. Baliga ‘833 describes a power semiconductor device in which the
height of a mesa is greater than the width of the mesa (col. 7, ll. 56-63; col.
9, ll. 61-63).

PRINCIPLES OF LAW
Anticipation
Anticipation of a claim under § 102 can be found only if the prior art
reference discloses every element of the claim. In re King, 801 F.2d 1324,
1326 (Fed. Cir. 1986).
Obviousness
The Examiner bears the initial burden of presenting a prima facie case
of obviousness. In re Oetiker, 977 F.2d 1443, 1445 (Fed. Cir. 1992). If that
burden is met, then the burden shifts to the Appellants to overcome the
prima facie case with argument and/or evidence. See Id.
A reference may not be antedated by a Rule 131 affidavit or
declaration that shows that Applicant had invented, prior to the reference
date, a part, some parts, or even a combination of parts, if the part or parts
are not within the scope of the claims being sought by Applicant. In re
Tanczyn, 347 F.2d 830, 833 (CCPA 1965).

Appeal 2008-005465
Application 10/929,590

7
ANALYSIS
Anticipation
We agree with Appellant’s argument (App. Br. 15-17) that polysilicon
plug 61 in Fujishima is not a field plate, and is merely an interconnect that
provides electrical connection between the drain electrode 52 at the surface
of the MISFET and the drain region 58 in the bottom of the trench (FF1).
Thus, the anticipation rejection of claims 36, 40 to 42, 45, and 47 is reversed
because Fujishima does not disclose every element of the claims. See King,
801 F.2d at 1326.
Obviousness
Turning first to claims 37 and 38, the obviousness rejection of these
claims is reversed because we agree with Appellant’s argument (App. Br.
17, 18) that neither Fujishima nor Lee describes a field plate disposed in a
trench as required by the claims (FF 2).
Turning to next to claims 46, and 48 to 50, we agree with Appellant’s
argument (App. Br. 24) that neither Fujishima nor Baliga ‘833 teaches or
suggests the noted field plate (FF 5).
Turning lastly, to claims 43 and 44, we find that Appellant has not
challenged the Examiner’s findings (Final Rej. 8, 9) that Baliga ‘372
describes all of the vertical high-voltage transistor structure set forth in these
claims (FF 3). The Rule 131 declaration submitted by Appellant to antedate
the November filing date of the Baliga ‘372 reference clearly shows a gate
poly and a field plate poly, but does not show a depth of the gate members
that is less than 20% of another vertical depth (FF 4). A measurement that is
“long” is not an indication of depth (FF 4). Accordingly, we find that
Appeal 2008-005465
Application 10/929,590

8
Appellant’s declaration does not prove that he invented the claimed vertical
depths prior to the date of the reference to Baliga ‘372. See Tanczyn, 347
F.2 at 833.
Appellant’s arguments throughout the briefs convince us of error in
the Examiner’s positions in the rejections of claims 36 to 38, 40 to 42, and
45 to 50. Oetiker, 977 F.2d at 1445. The evidence submitted by Appellant
is not sufficient to antedate the reference applied by the Examiner in the
rejection of claims 43 and 44.

CONCLUSIONS OF LAW
Anticipation
Appellant has demonstrated that the Examiner erred by finding that
polysilicon plug 61 in Fujishima is a field plate as set forth in claims 36, 40
to 42, 45, and 47.
Obviousness
Appellant has demonstrated that the Examiner erred by finding that
the applied references to Fujishima and Lee describe a field plate disposed in
a trench as required by claims 37 and 38.
Appellant has not demonstrated that the Examiner erred by finding
that the Rule 131 declaration is insufficient to remove the Baliga ‘372
reference from consideration as prior art in the obviousness rejection of
claims 43 and 44.
Appellant has demonstrated that the Examiner erred by finding that
the applied references to Fujishima and Baliga ‘833 teach a filed plate as set
forth in claims 46, and 48 to 50.
Appeal 2008-005465
Application 10/929,590

9
ORDER
The rejections of claims 36 to 38, 40 to 42, and 45 to 50 are reversed.
The obviousness rejection of claims 43 and 44 is affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

AFFIRMED-IN-PART

KIS

THE LAW OFFICES OF BRADLEY J. BEREZNAK
800 WEST EL CAMINO REAL
SUITE 180
MOUNTAIN VIEW, CA 94040