Ex Parte Dieffenderfer et al

Patent Trial and Appeal Board

Dec 21, 2016

11336357 (P.T.A.B. Dec. 21, 2016)

United States Patent and Trademark Office
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O.Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
11/336,357 01/20/2006 James Norris Dieffenderfer 050379 3727
23696 7590 12/23/2016
OTTAT mMM TNmRPORATFD
EXAMINER
5775 MOREHOUSE DR.
SAN DIEGO, CA 92121
ROCHE, JOHN B
ART UNIT PAPER NUMBER
2184
NOTIFICATION DATE DELIVERY MODE
12/23/2016 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
us-docketing@qualcomm.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte JAMES NORRIS DIEFFENDERFER,
JEFFREY TODD BRIDGES, MICHAEL SCOTT McILVAINE,
and THOMAS ANDREW SARTORIUS
Appeal 2015-001785
Application 11/336,357
Technology Center 2100
Before MICHAEL J. STRAUSS, JOHN R. KENNY, and
AARON W. MOORE, Administrative Patent Judges.
MOORE, Administrative Patent Judge.
DECISION ON APPEAL
Appeal 2015-001785
Application 11/336,357
STATEMENT OF THE CASE
Appellants1 appeal under 35 U.S.C. § 134(a) from a Final Rejection of
claims 1—28. We have jurisdiction under 35 U.S.C. § 6(b).
We reverse.
THE INVENTION
The application is directed to “techniques for processing instructions
in a processor pipeline.” (Spec. 11.) Claim 1, reproduced below, is
exemplary:
1. A method of pipeline operation, comprising:
initiating a fetch of a group of two operands specified in an
instruction, wherein one operand is to be conditionally selected
from the group of two operands based on an operand conditional
selection criterion in the instruction that specifies a condition
code, and the not selected one of the two operands is in flight in
the pipeline and not available at the time the fetch is initiated;
determining a value of the condition code affected by
execution of a previous function instruction in an execution
pipeline stage, that meets the operand conditional selection
criterion, and in response selects the one operand from the group
of two operands;
executing the instruction once the one selected operand has
been received; and
terminating the fetch in effect for the operand from the group
that is not selected before the non-selected operand becomes
available.
1 Appellants identify Qualcomm Incorporated as the real party in interest.
(See App. Br. 3.)
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Appeal 2015-001785
Application 11/336,357
REFERENCES
The prior art relied upon by the Examiner in
appeal is:
rejecting the claims
Sharangpani et al. US 5,699,537 Dec. 16, 1997
Bates et al. US 5,812,836 Sept. 22, 1998
Sheaffer US 2003/0191928 Al Oct. 9, 2003
Peng et al. US 6,633,971 B2 Oct. 14, 2003
Nair et al. US 2004/0111587 Al June 10, 2004
Hoyle et al. US 2005/0188182 Al Aug. 25, 2005
Sunayama et al. US 2005/0188187 Al Aug. 25, 2005
THE REJECTIONS
1. Claims 1-7, 10, 11, 13, 14, 16-19, 21, 22, and2A-27 stand
rejected under 35 U.S.C. § 103(a) as unpatentable over Sharangpani, Bates,
and Sunayama. (See Final Act. 2—13.)
2. Claims 8, 15, and 23 stand rejected under 35 U.S.C. § 103(a) as
unpatentable over Sharangpani, Bates, Sunayama, and Sheaffer. (See Final
Act. 13-14.)
3. Claims 9 and 20 stand rejected 35 U.S.C. § 103(a) as
unpatentable over Sharangpani, Bates, Sunayama, and Nair. (See Final Act.
14—16.)
4. Claim 12 stands rejected under 35 U.S.C. § 103(a) as
unpatentable over Sharangpani, Bates, Sunayama, and Peng. (See Final Act.
16-17.)
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Application 11/336,357
5. Claim 28 stands rejected under 35 U.S.C. § 103(a) as
unpatentable over Sharangpani, Bates, Sunayama, and Hoyle. (See Final
Act. 17-19.)
ANALYSIS
The claimed invention concerns a method of processing “to minimize
the number of stalls that may occur when executing instructions.” (Spec. |
4.) “The method involves detecting an instruction that specifies at least one
operand to be selected from a group of at least two operands, at least one of
which may be in flight in the pipeline.” (Id. | 5.) “[A]n operand selection
criterion that is specified by the instruction” is determined and “then
evaluated to select at least one operand from the group of at least two
operands.” (Id.) “The instruction may then be committed for execution
once the at least one selected operand is available without waiting for a non-
selected operand to become available.” (Id.) Essentially, the instruction
specifies a criterion that may allow an instruction to be committed for
execution even though an operand is not available.
All of the rejections are premised on the combination of Sharangpani
and Bates. Appellants argue “[t]he final Official Action does not show how
the technique used by Bates can be applied to any advantage by
Sharangpani, and [that]. . . such a combination would not be obvious to one
of ordinary skill in the art.” (App. Br. 33.) We agree.
The cited portions of Sharangpani describe a method of instruction
processing in which the locations of the operands for a given instruction are
identified and “execution core control logic” looks in a register file for the
operands. (Sharangpani 10:33—38.) In parallel, the execution core control
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Application 11/336,357
logic snoops local bypasses and the load/store execution return to determine
if the data is in either of those two locations. {Id. at 10:42-45.) Once the
location of the operand(s) are identified, a multiplexor is used to select the
desired signal. {Id. at 10:45—50.) Sharangpani thus teaches a system that
looks for the operands in the local bypasses and the load/store execution
cluster return to reduce latency and improve scalability as compared to
exclusive use of global bypasses in the prior art system shown in its Figure
1. {Id. at 10:33—62.) Sharangpani does not teach a system that, depending
on a criterion in the instruction, may execute the instruction upon receipt of
one operand and terminate any fetch for a non-selected operand before it is
received. Instead, Sharangpani seeks to ensure that all operands are
available as early as possible.
Bates teaches a new type of instruction that allows for a simpler
implementation of, for example, Bresenham’s Line Algorithm, which is used
for plotting a straight line in a display system. (Bates 3:51—54.) According
to Bates, the algorithm is conventionally implemented as a “basic bifurcated
code loop which [a]s illustrated employs two parallel paths, one of which is
chosen dependent on the state of the negative ALU status flag, ‘n’.” (Id. at
4:13—15.) “At each stage in the plotting process the program has to add a
selected augend (K1 or K2) depending on the state of one of the processor
flags (here the negative sign flag n).” {Id. at 4:30—32.) The improvement is
described as follows:
[A] processor (e.g., a display processor) in accordance with the
invention is capable of performing a new type of instruction
which we shall term here a ‘Selective Add’ (SADD) instruction.
The Selective Add (SADD) instruction differs from a normal
Add in that it effectively has three operands, although only two
are named in the instruction and two are used in execution. The
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Application 11/336,357
two operands named in the instruction are the augend and the
first of two possible addends (normally contained in the even of
an implied even/odd register pair). The two operands used in
execution are the augend and one of the two possible addends,
the selection of which addend is to be used being determined dy­
namically by the current setting of the negative ALU status flag.
{Id. at 4:54—67.) Bates also does not teach a system that, depending on a
criterion in the instruction, may execute the instruction upon receipt of one
operand and terminate any fetch for a non-selected operand before it is
received. Instead, Bates uses two operands, R1 and either R2 or R3.
The Examiner provided the following analysis regarding the
motivation to combine:
At the time of the invention, it would have been obvious to
one of ordinary skill in the art, having the teachings of Sha-
rangpani ’537 and Bates ’836 before him or her, to modify the
pipelined processor of Sharangpani ’537 to include the operand
selection criterion and commitment of an instruction for execu­
tion of Bates ’836 by using the instruction source identifiers of
Sharangpani ’537 to determine whether the operands to be se­
lected are currently in use by another instruction, and by using
the multiplexor to select data from a register if the operand is not
currently being used by another instruction.
The motivation for doing so would have been that in contem­
porary processing systems, iterative tasks would require signifi­
cant amounts of processing (column 1, lines 44-46).
(Ans. 4.)
We, however, fail to see why one of skill in the art would have been
motivated to modify Sharangpani (which selects the best available data
location) to use Bates’ conditional selection (which uses a first operand and
one of two possible second operands in order to implement a particular type
of algorithm). The Examiner’s stated motivation—“in contemporary
processing systems, iterative tasks would require significant amounts of
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processing”—reflects the general idea that efficiencies are desirable, but
fails to provide a rational reason for making this particular combination.
Sharangpani already selects the most readily available source for the
operands and it is unclear from the rejection how Bates’s techniques might
improve source selection. While it may be an advantage for a processor to
“determine whether the operands to be selected are currently in use by
another instruction” and “us[e] [a] multiplexor to select data from a register
if the operand is not currently being used by another instruction,” we fail to
see how Bates would suggest or provide that advantage, as it selects between
R2 or R3 to implement a particular algorithm in a way that avoids an extra
loop,2 not because R2 or R3 are in use.
We accordingly conclude that the combination lacks the support of a
sufficient rational underpinning, and, thus, do not sustain the Section 103
rejections of claims 1—28, all of which are based on the combination of
Sharangpani and Bates.3
2 See Bates 5:56—67 (“In this example, the SADD instruction specifies as
register addresses the addresses R1 and R2 on the lines 28 and 29
respectively, the address of register R2 being chosen to be an even register
address. If, then, the sign flag of the condition register is set negative, the
combination of the SADD decode signal from the decoder output 40 and the
set sign flag causes the output of the AND gate 27 to go high and the output
of the OR gate 33 to be logical 1 (for an odd address), even though the
lowest bit from the SADD instruction was for an even address. In this way
the R2 address from the SADD instruction is modified to the address of
register R3.”).
3 Because this issue is fully dispositive of the appeal, we do not reach
Appellants’ other arguments.
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DECISION
The rejections of claims 1—28 are reversed.
REVERSED
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