Ex Parte DeCenzo

Board of Patent Appeals and Interferences

Nov 1, 2011

11147137 (B.P.A.I. Nov. 1, 2011)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
11/147,137 06/07/2005 David Peter DeCenzo STL12403 6622
7590 11/01/2011
Fellers, Snider, Blankenship,
Bailey & Tippens, P.C.
100 North Broadway, Ste. 1700
Oklahoma City, OK 73102-8820
EXAMINER
LO, KENNETH M
ART UNIT PAPER NUMBER
2189
MAIL DATE DELIVERY MODE
11/01/2011 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)

UNITED STATES PATENT AND TRADEMARK OFFICE
________________
BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
________________

Ex parte DAVID PETER DECENZO
________________

Appeal 2010-004118
Application 11/147,137
Technology Center 2100
________________

Before THOMAS S. HAHN, ELENI MANTIS MERCADER, and
CARL W. WHITEHEAD, JR., Administrative Patent Judges.

HAHN, Administrative Patent Judge.

DECISION ON APPEAL
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Appellant invokes our review under 35 U.S.C. § 134(a) from the final
rejection of claims 1-21. We have jurisdiction under 35 U.S.C. § 6(b). An
oral hearing was held on October 18, 2011. We affirm-in-part.

STATEMENT OF THE CASE
Appellant claims an apparatus that includes a plurality of local data
storage units with each unit having a local programmable processor. The
local data storage units are interconnected through a shared resource module
that has a memory for storing a shared programming instruction set executed
by each local programmable processor.1 Independent claims 1 and 10 are
illustrative:
1. An apparatus comprising a plurality of local data storage units each
comprising a local control circuit and a housing which encloses a
moveable data transducer adjacent a data storage medium, and a
shared resource module which physically interconnects each of said
plurality of local units, the shared resource module comprising first
means for providing resources required by the local control circuits to
transfer data to and from said data storage media.
10. An apparatus comprising:
a plurality of data storage units each comprising a local programmable
processor and a housing which encloses a moveable data transducer
adjacent a data storage medium; and
a shared resource module which physically interconnects each of the
plurality of data storage units, the module comprising a memory space
that stores a shared programming instruction set executed by each said
local programmable processor.

1 See generally Spec. 3:24-27; 4:8-9; 5:5-11, 29-31; 6:3-15; Figs. 1-3.
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Rejection
The Examiner rejected claims 1-21 under 35 U.S.C. § 103(a) as
unpatentable over Fujimoto (US 2004/0153721 A1; Aug. 5, 2004) and
Shafe’ (US 5,918,068; June 29, 1999) (Final Action 2-15).

PRINCIPLES OF LAW
Examined claim terms are given their broadest reasonable meaning
utilizing ordinary usage as such claim terms would be understood by one
skilled in the art by way of definitions and the written description. In re
Morris, 127 F.3d 1048, 1054 (Fed. Cir. 1997).
The claims, of course, do not stand alone. Rather, they
are part of a “fully integrated written instrument” consisting
principally of a specification that concludes with the claims.
For that reason, claims “must be read in view of the
specification, of which they are a part.” . . . [T]he specification
“is always highly relevant to the claim construction analysis.
Usually, it is dispositive; it is the single best guide to the
meaning of a disputed term.”
Phillips v. AWH Corp., 415 F.3d 1303, 1315 (Fed. Cir. 2005) (citations
omitted). “Though understanding the claim language may be aided by the
explanations contained in the written description, it is important not to
import into a claim limitations that are not a part of the claim.” SuperGuide
Corp. v. DirecTV Enters., Inc., 358 F.3d 870, 875 (Fed. Cir. 2004).
In the circumstance of a claimed element using language falling under
the scope of 35 U.S.C. § 112, sixth paragraph (e.g., means-plus-function
language), the Specification must be consulted to interpret that language by
determining the structure corresponding to the recited function. In re
Donaldson Co., Inc., 16 F.3d 1189, 1193 (Fed. Cir. 1994). In particular,
claim language expressed in means-plus-function language “shall be
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construed to cover the corresponding structure . . . described in the
specification and equivalents thereof.” 35 U.S.C. § 112, sixth paragraph.
Appellant’s Contentions2
Appellant first argues patentability for independent claim 10 (App. Br.
7-12). Appellant contends that the recited “memory space that stores a
shared programming instruction set executed by each . . . local
programmable processor” is incorrectly construed by the Examiner “to cover
. . . duplicate sets of programming code stored in each memory 143/144 of
each disc control portions 140 of Fujimoto ‘721” (App. Br. 8). Appellant
also contends that combining Fujimoto with Shafe’ does not avoid or
overcome the asserted error in claim interpretation (App. Br. 11-12).
Appellant next argues independent claim 16 (App. Br. 12-15).
Appellant contends that the recited “shared memory space that stores data to
be written . . . or retrieved . . . , said data transferred . . . without being stored
in an intermediary memory space” is not taught by the cited references.
These references are asserted to teach providing local buffers for data
transfers (App. Br. 14-15).
Appellant then argues independent claim 1 (App. Br. 16-18).
Appellant contends the Examiner erred in concluding that a prior art taught
communication interface interconnection is read on by the recited “means

2 Arguments that Appellant could have made but did not make in the Brief
or Reply Brief have not been considered and are deemed to be waived. See
37 C.F.R. § 41.37(c)(1)(vii). Further, at an oral hearing an “[A]ppellant may
only . . . present argument that has been relied upon in the [B]rief or [R]eply
[B]rief except as permitted by paragraph (e)(2) of this section.” 37 C.F.R. §
41.47(e)(1). No exception to argue beyond the Brief or Reply Brief
presented arguments has been requested.
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for providing resources required by the local control circuits to transfer data
to and from . . . data storage media” (App. Br. 17).
Appellant groups dependent claims 3, 11, and 18, and separately
argues claim 3 as a representative claim (App. Br. 18). Appellant asserts the
Examiner erred in concluding that claim 3 reads on a Shafe’ taught hard disc
controller (HDC) supplying data unit local processors with servo code (App.
Br. 19). Appellant relies on the claim 3 recited storing of a shared program
instruction set that includes servo code as distinguishing over Shafe’, which
is asserted as failing to teach or suggest “use of servo code in a shared
programming instruction set as claimed” (id.).
Appellant groups claims 4 and 12, and separately argues claim 4 as a
representative claim (id.). Appellant contends the Examiner failed to
identify any prior art teaching or suggestion for the claim 4 recited “peer-to-
peer arbitrated bus between the memory space and each of the local
programmable processors, . . . wherein said processors concurrently arbitrate
access to the programming instruction set during operation of the apparatus”
(id.).

ISSUES
1. Did the Examiner err under 35 U.S.C. § 103(a) in concluding that the
cited references teach or suggest the claim 10 recited “memory space
that stores a shared programming instruction set executed by each . . .
local programmable processor”?
2. Did the Examiner err under 35 U.S.C. § 103(a) in concluding that the
cited references teach or suggest the claim 16 recited “shared memory
space that stores data to be written . . . or retrieved . . . , said data
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transferred . . . without being stored in an intermediary memory
space”?
3. Did the Examiner err under 35 U.S.C. § 103(a) in concluding that the
cited references teach or suggest the claim 1 recited “means for
providing resources required by the local control circuits to transfer
data to and from . . . data storage media”?
4. Did the Examiner err under 35 U.S.C. § 103(a) in concluding that the
cited references teach or suggest the claim 3 covered memory space
storing a shared program instruction set that includes servo code to
control each local unit?
5. Did the Examiner err under 35 U.S.C. § 103(a) in concluding that the
cited references teach or suggest the claim 4 recited “peer-to-peer
arbitrated bus between the memory space and each of the local
programmable processors, . . . wherein said processors concurrently
arbitrate access to the programming instruction set during operation of
the apparatus”?

ANALYSIS
Claim 10
Appellant separately argues independent claim 10 (App. Br. 7-12;
Reply Br. 3).3 Appellant contends, as identified supra, that the recited
“memory space that stores a shared programming instruction set executed by

3 In the Appeal Brief, Appellant argues claim 10 under the heading “Claims
10-15” (App. Br. 7). In other sections of the Appeal Brief, however,
Appellant argues claims 11 and 12 (App. Br. 18-19). Accordingly, claims
11 and 12 are addressed infra and dependent claims 13-15, which are not
separately argued, are addressed in this section of the opinion.
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each said local programmable processor” is incorrectly construed by the
Examiner “to cover . . . duplicate sets of programming code stored in each
memory 143/144 of each disc control portions 140 of Fujimoto ‘721” (App.
Br. 8).
The Examiner finds that Fujimoto teaches the claim 10 recited
“module comprising a memory space that stores a shared programming
instruction set executed by each said local programmable processor” (Ans.
17). The Examiner finds Fujimoto discloses:
“When various kinds of programs stored in the memory 143 or
the [non-volatile random access memory] NVRAM 144 are
executed, the function of the disk control portion 140 according
to this embodiment can be implemented. Examples of the
function implemented by the disk control portion 140 are
control of the storage devices” (Paragraph 0091). The
NVRAM stores the share programming instruction set in
Fujimoto. Additionally, the shared programming instruction set
is executed by each said local processor.
(Ans. 17-18 (brackets omitted)). Appellant does not dispute that Fujimoto
includes the quoted disclosures. We confirm that it does.
Appellant’s focused dispute is that the claim 10 “language recites just
a single memory space that stores a single set that is executed by all N
processors” instead of the Fujimoto taught programming set executed by
each local processor (App. Br. 8). Appellant particularly points out and
argues:
[The] construction of claim language offered by an Examiner
that is directly contrary to the specification is not a reasonable
interpretation, and is therefore an improper construction.
Phillips v. AWH Corp., 75 USPQ2d 1321 (Fed. Cir. 2005)(en
banc); MPEP 2111. The skilled artisan would not construe the
term “shared programming instruction set executed by each
said local programmable processor” as covering duplicate
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copies that are separately stored and executed as in Fujimoto
‘721, since the claimed combination serves to eliminate the
need to provide such multiple sets of code in multiple storage
locations.
(App. Br. 8-9). Appellant continues with citations to Specification
disclosures and discussions of those disclosures (see App. Br. 9-11).
The Examiner directly responds:
The Claims do not present any limitation in regards to storing
the shared programming instruction set only within . . . “a
memory space” of the module nor does it require any limitation
with regards to from where the shared programming
instruction set is executed. Appellant is attempting to argue
that the limitations within the specification require that this
shared instruction set not be copied and separately stored for
execution by the processors, however as pointed out by the
multiple sections of the specification quoted by Appellant, these
limitations exist only within the specification and not within the
claim language itself. Within the system of Fujimoto and
Shafe, the shared programming instruction set is executed by
each said local processor, and is stored in a memory space of
the module as required by the claim.
(Ans. 18-19). Appellant responds:
[T]he skilled artisan would immediately understand the claim term
“shared programming instruction set” to be defined by the
specification as specifically eliminating the need for the use of
individual stores for the processors. There is no need to “add” the so-
called missing language from the specification to the claim because
this subject matter is already present in the claim.
(Reply Br. 3).
We disagree with Appellant’s contention that the Examiner
misconstrued the disputed claim 10 limitation. In particular, from our
review of the record we disagree that the recited “shared programming
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instruction set” is “defined by the specification” (Reply Br. 3); instead, we
find this element is merely described in context with an embodiment (see
Spec. 5:29–6:8; 7:30-33). In particular, as identified by the Examiner, we do
not find that claim 10 recites any limitation restricting the shared
programming set to be only stored within a shared resource module memory
space, or that claim 10 recites any limitation that requires where the shared
programming set is to be executed (see Ans. 18). Consequently, we do not
find Appellant’s proffered construction to be part of claim 10, and we agree
with the Examiner’s interpretation. See SuperGuide, 358 F.3d at 875.
Appellant further argues that combining Fujimoto with Shafe’ does
not avoid or overcome the asserted error in claim interpretation (App. Br.
11-12). As addressed supra, we do not find the Examiner misconstrued the
disputed claim limitation, and, therefore, we do not agree with Appellant’s
conclusion that the Examiner’s combination of references is flawed.
For the foregoing reasons, we sustain the rejection of independent
claim 10, and, for the same reasons, we sustain the rejection of dependent
claims 13-15, which are not separately argued.
Claim 16
Appellant separately argues independent claim 16 (App. Br. 12-15;
Reply Br. 6-7).4 Appellant contends, as identified supra, that the recited
“shared memory space that stores data to be written . . . or retrieved . . . ,
said data transferred . . . without being stored in an intermediary memory

4 In the Appeal Brief, Appellant argues claim 16 under the heading “Claims
16-21” (App. Br. 12). In other sections of the Appeal Brief, however,
Appellant argues claim 18 (App. Br. 18-19). Accordingly, claim 18 is
addressed infra and dependent claims 17 and 19-21, which are not separately
argued, are addressed in this section of the opinion.
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space” is not taught by the cited references, which instead teach providing
local buffers for data transfers (App. Br. 14-15).
The Examiner finds the disputed limitation taught in Fujimoto in
paragraphs [0056-0057] (Ans. 13-14). Appellant disputes the Examiner’s
finding by generally contending that Fujimoto utilizes local buffers to store
data during data transfers (App. Br. 14). Appellant argues Fujimoto
“transfers the data to the local storage units 300 for storage” (App. Br. 14-
15). We are not persuaded by this argument because the Examiner finds, as
do we, that the claim 16 recited “plurality of data storage units” read on the
Fujimoto storage devices 300 (Ans. 13; see Fujimoto ¶ [0090]). Data is
ultimately transferred to and from the Fujimoto storage devices 300, but
Appellant has not established that the Fujimoto teaching relied on by the
Examiner (¶¶ [0056-0057]) employs or fairly suggests using local
intermediary memory devices for data transfers.
Appellant further contends that Shafe’ utilizes local buffers to store
data during data transfers (App. Br. 14). We do not find that the record
supports this conclusion. Irrespective of such argument, however, the
Examiner relies on Fujimoto for teaching the disputed limitation (Ans. 13-
14). The Examiner instead relies on Shafe’ for teaching “a plurality of data
storage units each comprising a local programmable processor and a housing
which encloses a moveable data transducer adjacent a data storage medium”
(Ans. 14). We also do not find evidence that Shafe’ in any way criticizes,
discredits, or discourages trying the disputed limitation subject matter taught
by Fujimoto so as to lead an ordinarily skilled artisan away from the
combination of references. Accordingly, we are not persuaded by
Appellant’s contentions.
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For the foregoing reasons, we sustain the rejection of independent
claim 16, and, for the same reasons, we sustain the rejection of dependent
claims 17 and19-21, which are not separately argued.
Claim 1
Appellant separately argues independent claim 1 (App. Br. 16-18;
Reply Br. 3-5).5 Appellant contends, as identified supra, that the Examiner
erred in concluding that a prior art taught communication interface
interconnection is read on by the recited “means for providing resources
required by the local control circuits to transfer data to and from . . . data
storage media” (App. Br. 17).
It is not disputed that the argued claim 1 limitation is drafted in
means-plus-function format as authorized in 35 U.S.C. § 112, sixth
paragraph. Accordingly, the Examiner interprets the recited “means for
providing resources . . .” by consulting the Specification and finds:
Appellant[’]s specification states “The module 122 supports
what is referred to herein as subgroup, or shared circuitry 128,
described below. Connector 130 and ribbon cable assembly
132 interconnect the circuitry 128 to other components of a
computer network.” ([Spec. 4:8-10]). As the claims do not
limit “provided resources” the only thing required is an
interface to the component of the network that will provide the
resources (wire or interface) required to transfer data to and
from storage media.
(Ans. 23-24).

5 In the Appeal Brief, Appellant argues claim 1 under the heading “Claims
1-9” (App. Br. 16). In other sections of the Appeal Brief, however,
Appellant argues claims 3 and 4 (App. Br. 18-19). Accordingly, claims 3
and 4 are addressed infra and dependent claims 2 and 5-9, which are not
separately argued, are addressed in this section of the opinion.
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Citing Donaldson, 16 F.3d at 1195, Appellant quotes that “[t]he PTO
may not disregard the structure disclosed in the specification corresponding
to such language when rendering a patentability determination” (Reply Br. 3
(emphasis omitted)). The Examiner, according to Appellant, disregards
Specification disclosed structure corresponding to the recited “first means.”
Appellant specifically contends that the Specification disclosure for “shared
resource module circuitry 128 of FIGS. 3-4” is the structure corresponding
to the recited function (App. Br. 16), which is “providing resources required
by the local control circuits to transfer data to and from said data storage
media.” Without correlating to any recited functional limitations, Appellant
asserts as a conclusion that “the Examiner has disregarded that the
communications interface fails to perform the identical function specified in
the claim in substantially the same way, and fails to produce substantially
the same results as the shared module circuitry 128 disclosed in the
specification” (Reply Br. 4 (citation omitted)). Further, Appellant contends
that the recited function must be narrowed to the identified Specification
disclosed “shared module circuitry 128” and as such “[t]he Examiner is
bound to this determination and cannot substitute his own” (id.).
We agree with the Examiner that a reasonably broad interpretation of
the recited “providing resources required by the local control circuits” is a
“(wire or interface) required to transfer data to and from storage media”
(Ans. 23-24), which is a Specification disclosed effectuating structure (see
Spec. 4:8-10). Our reviewing Court has held that in accordance with 35
U.S.C. § 112, sixth paragraph, the Specification must be consulted to
interpret means-plus-function language by determining structure
corresponding to claimed function. Donaldson, 16 F.3d at 1193. The Court,
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however, further held that this requirement “does not conflict with the
general claim construction principle that limitations found only in the
specification . . . should not be imported or read into a claim.” Donaldson,
16 F.3d at 1195. Accordingly, we disagree that the Examiner substituted his
determination or is bound by Appellant’s determination that would import
structure into the claim that is not supported by claimed narrowing
functional language.
For the foregoing reasons, we sustain the rejection of independent
claim 1, and, for the same reasons, we sustain the rejection of dependent
claims 2 and 5-9, which are not separately argued.
Claims 3, 11, and 18
Appellant separately argues claim 3 (App. Br. 18-19). Appellant
contends, as identified supra, that the Examiner erred in concluding that
claim 3 reads on a Shafe’ taught HDC supplying data unit local processors
with servo code (App. Br. 19). Appellant relies on the claim 3 recited
storing of a shared program instruction set that includes servo code as
distinguishing over Shafe’, which is asserted as failing to teach or suggest
“use of servo code in a shared programming instruction set as claimed” (id.).
The Examiner relies on a finding that Shafe’ teaches an HDC
including “servo control” (Ans. 6, 24). We agree with Appellant that based
on the record an ordinarily skilled artisan would understand that the Shafe’
HDC supplies servo control for local processors and the recited
“programming instruction set comprises servo code” does not read on the
Shafe’ HDC (App. Br. 19). Accordingly, we do not sustain the rejection of
claims 3, 11, and 18, which all recite the same substantive limitation.
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Claims 4 and 12
Appellant separately argues claim 4 (App. Br. 19). Appellant
contends, as identified supra, that no prior art teachings or suggestions are
identified for the claim 4 recited “peer-to-peer arbitrated bus between the
memory space and each of the local programmable processors, . . . wherein
said processors concurrently arbitrate access to the programming instruction
set during operation of the apparatus” (id.).
The Examiner responds:
Fujimoto discloses, “The interface portion 141 has a
communication interface for communicating with the channel
control portions 110, etc. through the connection portion 150,
and a communication interface for communicating with the
storage devices 300” (Paragraph 0090). As is clearly shown,
the interface provides communication between t[w]o peers,
without the requirement of an arbitrator. The devices
communicate, via the communications interface, directly. The
claim requires, “wherein the shared resource module further
comprises a peer-to-peer arbitrated bus between the memory
space and each of the local programmable processors, and
wherein said processors concurrently arbitrate access to the
programming instruction set during operation of the
apparatus[.”] The system of Fujimoto and Shafe, during the
operation of the apparatus, receive the shared programming
instruction set from the NVRAM at each of the processors in
the physical disks over a connection portion 150 and a single
communication interface for communicating with the storage
devices. It is inherent that the communication is arbitrated by
the peers on the bus.
(Ans. 24-25). Appellant is silent and does not contest the Examiner’s
explained finding and conclusion.
Based on our review of the record, we also find the Examiner has
relied on what Fujimoto discloses, and we conclude that the Examiner has
reasonably relied on the Fujimoto teaching to conclude that the subject
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limitation reads on Fujimoto. Accordingly, we disagree with Appellant’s
contention that prior art fails to teach the disputed limitation.
For the foregoing reasons, we sustain the rejection of claims 4 and 12.

ORDER
The Examiner’s decision rejecting claims 1, 2, 4-10, 12-17, and 19-21
is affirmed. The Examiner’s decision rejecting claims 3, 11, and 18 is
reversed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

AFFIRMED-IN-PART

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