Ex Parte Deaton

Board of Patent Appeals and Interferences

Jun 13, 2011

10949041 (B.P.A.I. Jun. 13, 2011)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________________

Ex parte CRAIG F. DEATON

____________________

Appeal 2009-008271
Application 10/949,041
Technology Center 2100
____________________

Before ST. JOHN COURTENAY III, THU A. DANG, and DEBRA K.
STEPHENS, Administrative Patent Judges.

DANG, Administrative Patent Judge.

DECISION ON APPEAL

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I. STATEMENT OF CASE
Appellant appeals the Examiner’s second rejection of claims 1-19
under 35 U.S.C. § 134(a). We have jurisdiction under 35 U.S.C. § 6(b).
We affirm.

A. INVENTION
According to Appellant, the invention relates to the development and
testing of new complex semiconductor products and more specifically for
testing the “correctness” of the logic or verification environment before the
product or device is released and available for testing (Spec. 1, ¶ [0002]).

B. ILLUSTRATIVE CLAIM
Claim 1 is exemplary and reproduced below:

1. A method of testing the correct operation of the logic
environment associated with a selected device or component
comprising the steps of:

providing a virtual device or component representative of
said selected device, said virtual device for receiving input logic
signals and for providing output logic signals;

generating signals representative of selected logic inputs
to said selected device and providing said logic inputs to said
virtual device;

monitoring selected logic outputs and said selected logic
inputs of said virtual device;

predicting said selected logic outputs of said selected
device as a function of said selected logic inputs;

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driving said selected logic outputs to be the same as said
predicted logic outputs; and

comparing said monitor of logic outputs to said predicted
logic outputs to determine if they are the same.

C. REJECTIONS
The prior art relied upon by the Examiner in rejecting the claims on
appeal is:

West US 5,475,624 Dec. 12, 1995

Claims 1-19 stand rejected under 35 U.S.C. § 102(b) as being
anticipated by West.

II. ISSUE
Has the Examiner erred in finding that West teaches “comparing said
monitor of logic outputs to said predicted logic outputs to determine if they
are the same” (claim 1)?

III. FINDINGS OF FACT
The following Findings of Fact (FF) are shown by a preponderance of
the evidence.
West
1. West discloses creating two emulations of a logic circuit, one of
which is a “good” model containing no faults and the other of which
is a “faultable” model into which possible faults may be selectively
introduced (col. 4, ll. 45-48).
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2. The device output signals 735 of “good” device emulation 705 are
combined with the device output signals 830 of “faulted” device
emulation 815 in an exclusive-OR operation by XOR gate 835 to
produce a comparison signal 840 (col. 8, l1. 4-14; Fig. 8).

IV. ANALYSIS
For all of claims 1-19, Appellant merely repeats the language of
claims 1 and 11, merely states that the prior art “teaches comparing the
device output of good device emulation with device output signals of faulted
device emulation” and makes a statement that the cited reference “does not
show, teach, or suggest the above recited limitations of claims 1 and 11”
(App. Br. 11).
The Examiner finds that “inputs to and outputs from a logic circuit,
such as taught by West, make up logic inputs and logic outputs, as claimed”
wherein “any output from a logic device is a logic output” (Ans. 7).
According to the Examiner, “West does teach that the ‘faultable’ model is
monitored; in that, the model outputs are collected and compared with the
‘good’ model outputs to see if a difference is detected” wherein “the ‘good’
outputs of West must be correct and this knowledge must be known
beforehand” (Ans. 8). We find no error in the Examiner’s findings.
First, we find that Appellant’s statement which merely points out what
a claim recites will not be considered an argument for separate patentability
of the claim. See 37 C.F.R. § 41.37(c)(1)(vii). Moreover, Appellant’s mere
statement that the reference does not disclose the recited claim language but
that is unsupported by factual evidence is entitled to little probative value.
In re Geisler, 116 F.3d 1465, 1470 (Fed. Cir. 1997); see also In re De
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Blauwe, 736 F.2d 699, 705 (Fed. Cir. 1984); and Ex parte Belinne, No.
2009-004693, 2009 WL 2477843 at *3-4 (BPAI Aug. 10, 2009)
(informative). Accordingly, we find that, by merely pointing out what the
claim recites and making a conclusory statement that the reference does not
disclose the recited claim language without support by factual evidence
(App. Br. 11) in response to the Examiner’s detailed findings (Ans. 7-8),
Appellant has not shown error in the Examiner’s findings.
Furthermore, we find no error in the Examiner’s finding that West
teaches “comparing said monitor of logic outputs to said predicted logic
outputs to determine if they are the same” (claim 1 and similarly recited in
claim 11). In particular, we give the claims their broadest reasonable
interpretation consistent with the Specification without reading limitations
from the Specification into the claims. See In re Bigio, 381 F.3d 1320, 1324
(Fed. Cir. 2004) and In re Van Geuns, 988 F.2d 1181, 1184 (Fed. Cir. 1993).
Claim 1 (or similarly recited claim 11) does not place any limitation
on what the term “monitor of logic outputs” or “predicted logic outputs”
means other than the two outputs are compared “to determine if they are the
same.” Thus, we give “monitor of logic outputs” its broadest reasonable
interpretation as outputs related to a logic circuit that is being monitored.
Similarly, we interpret “predicted logic outputs” as outputs related to a logic
circuit that is known beforehand.
West discloses creating a “good” model of a logical circuit containing
no faults and a “faultable” model of the logical circuit into which possible
faults may be selectively introduced (FF 1), wherein the output signals of
“good” model is compared with the output signals of “faultable” model (FF
2). We find the output signals of the models of the logical circuit to be
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“logic outputs,” and thus find the “predicted logic outputs” to read on West’s
“good” model outputs that are known beforehand (and are predetermined to
be without faults). That is, we agree with the Examiner that “the ‘good’
outputs of West must be correct and this knowledge must be known
beforehand” (Ans. 8).
Furthermore, we find no error in the Examiner’s finding that “West
does teach that the ‘faultable’ model is monitored; in that, the model outputs
are collected and compared with the ‘good’ model outputs to see if a
difference is detected” (id.). That is, we find no error in the Examiner’s
finding that the “monitor of logic outputs” to read on West’s “faultable”
model outputs that are being monitored.
Accordingly, we find no error in the Examiner’s finding that
representative claim 1, independent claim 11 falling therewith, and claims 2-
10 and 12-19 depending respectively therefrom are anticipated by West.

V. CONCLUSION AND DECISION
The Examiner’s decision rejecting claims 1-19 under 35 U.S.C. §
102(b) is affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

AFFIRMED

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