Ex Parte De Greef

Patent Trial and Appeal Board

Sep 27, 2012

10587604 (P.T.A.B. Sep. 27, 2012)

UNITED STATES PATENT AND TRADEMARKOFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
10/587,604 07/27/2006 Petrus Maria De Greef E5982-00305 3561
77561 7590 09/28/2012
Duane Morris LLP (Entropic)
IP Department
30 South 17th Street
Philadelphia, PA 19103-4196
EXAMINER
MARTELLO, EDWARD
ART UNIT PAPER NUMBER
2628
MAIL DATE DELIVERY MODE
09/28/2012 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)

UNITED STATES PATENT AND TRADEMARK OFFICE
________________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
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Ex parte PETRUS MARIA DE GREEF
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Appeal 2010-005031
Application 10/587,604
Technology Center 2600
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Before BRADLEY W. BAUMEISTER, JEFFREY S. SMITH, and
STANLEY M. WEINBERG, Administrative Patent Judges.

BAUMEISTER, Administrative Patent Judge.

DECISION ON APPEAL

Appeal 2010-005031
Application 10/587,604

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SUMMARY
Appellant appeals under 35 U.S.C. § 134(a) from the Examiner’s
rejections of claims 1-11:
Claims 1-8 stand rejected under 35 U.S.C. § 103(a) as obvious over
Schiefer (EP 0 875 882 A2).
Claims 9-11 stand rejected under 35 U.S.C. § 103(a) as obvious over
Schiefer and Chen (US 2003/0164897 A1).
We have jurisdiction under 35 U.S.C. § 6(b).
We reverse.

OBVIOUSNESS REJECTION OF
CLAIMS 1-8 OVER SCHIEFER
The Examiner and Appellant dispute whether Schiefer suggests a
display system that sets the ratio between a display frame rate and a source
frame rate at 2:1, as required by each of claims 1-8. The Examiner found
that Schiefer sets a ratio between a display clock (DCLK) and an input video
clock (IPCLK) at 4:1. (Ans. 4.) The Examiner concluded that it would have
been obvious to alternatively set the ratio to the claimed value of 2:1,
particularly in view of the following determinations:
(i) Schiefer does not restrict the ratio to the disclosed value of 4:1. (Ans.
4, 14.)
(ii) It would have been a matter of “design choice” to set the ratio at 2:1,
if–as in Appellant’s disclosed invention–Schiefer’s system
implemented an “input image data rate [of] 1/2 half [sic] the screen
refresh rate of the video display.” (Ans. 13.)
Appeal 2010-005031
Application 10/587,604

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(iii) A skilled artisan would have accordingly set the ratio at 2:1, if
implementing an interlaced display format.1 (Id.)
According to this third determination, supra, the Examiner
alternatively finds that the cited embodiment implements an interlaced
display format and, accordingly, reasons that Schiefer would have employed
half as much scaling of the display clock (DCLK) if implementing a
progressive format. (See Ans. 13 (“[I]nterlaced formats can be easily
changed to a progressive format[.]”)).
Appellant responds, in part
. . . The large ratio between input and output clock rates
(“DCLK = 4*IPCLK”, see id. at Fig. 11) disclosed by Schiefer
and cited by the Examiner does not relate to the ratio between
the input and output frame rates. Rather, the 4:1 ratio discussed
in the Schiefer specification relates to the system horizontally
and vertically upscaling an input image by a factor of 2 for an
output video, while maintaining a locked, similar frame rate
through the control of the respective line rates (see id., at col.
21, lines 15-33 (discussing display line rate as a fractional
multiple of the input video main clock)). These line rates differ
due to the respective number of pixels per line in the input and
output images. See id., at col. 21, lines 34-46 (discussing
means to force frame locking so the resulting display frame
period is similar to the input video frame period.)
Schiefer, therefore, discloses a ratio for a clock rate,
which is different from and not suggestive of the frame rate of
the claimed subject matter.
(Reply Br. 5-6 (original emphasis); see also App. Br. 7-8.)

1 For background, we note that interlaced display formats input each of two
image fields at half the display frame rate, while progressive display formats
do not. See e.g., US 7,176,977 B2 to Zhu et al. (not of record), col. 1, ll. 20-
51.
Appeal 2010-005031
Application 10/587,604

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We agree with Appellant’s argument insofar that the Examiner has not
explained how Schiefer’s cited ratio between a display clock (DCLK) and
input video clock (IPCLK)–a ratio of pixel rates (Ans. 4, 14)–suggests the
claimed ratio between display and source frame rates. The alleged
correspondence is not self-evident from Schiefer’s cited embodiment, which
despite the scaled clock speeds (DCLK, IPCLK), is described as having
display and input video frame rates that are decouple[d], “match[ed] . . .
exactly,” or similar. (Schiefer, col. 18, ll. 20-25; col. 20, ll. 6-11; col. 21, ll.
15-20 and 24-28.)
In sum, the Examiner concludes that it would have been obvious to
implement the claimed ratio as a matter of “design choice,” e.g., as part of
implementing an interlaced display format. The Examiner’s reasoning is
neither meaningfully explained nor apparently consistent with the cited
record. Accordingly, the obviousness rejection of claims 1-8 over Schiefer
is not sustained.

OBVIOUSNESS REJECTION OF
CLAIMS 9-11 OVER SCHIEFER AND CHEN
Claims 9-11 depend from claim 2. Because the Examiner relies on
the above-noted reasoning in rejecting claims 9-11 (Ans. 16-17), we
likewise do not sustain the obviousness rejection of claims 9-11 over
Schiefer, and Chen for the reasons set forth above.

Appeal 2010-005031
Application 10/587,604

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DECISION
The Examiner’s decision rejecting claims 1-11 is reversed.

REVERSED

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