Ex Parte Davies et al

Board of Patent Appeals and Interferences

Mar 26, 2010

10710140 (B.P.A.I. Mar. 26, 2010)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________

Ex parte NORMAN DAVIES, DARRELL HATFIELD, FRANK
KATTWINKEL, and OWEN N. WELLS
____________

Appeal 2009-007623
Application 10/710,140
Technology Center 2100
____________

Decided: March 29, 2010
____________

Before JOSEPH L. DIXON, THU A. DANG, and
DEBRA K. STEPHENS, Administrative Patent Judges.

DIXON, Administrative Patent Judge.

DECISION ON APPEAL
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The Appellants appeal under 35 U.S.C. § 134(a) from the Final
Rejection of claims 1-8, 10, 14, and 16-21. Claims 9, 11-13, and 15 have
been canceled. We have jurisdiction under 35 U.S.C. § 6(b).
We affirm.

I. STATEMENT OF THE CASE
The Invention
The invention at issue on appeal relates to a method and system for
queuing interrupt messages (Abstract).
The Illustrative Claim
Claim 1, an illustrative claim, reads as follows:
1. A computer system, comprising:

a parallel communication bus; and

a first device operably coupled to the parallel communication
bus, the first device configured to receive first and second
interrupt messages transmitted through the parallel
communication bus to a first bus address associated with the
first device, the first and second interrupt messages each
comprising a plurality of bits;

the first device having a memory, a bridge communication
device, a processor, an interrupt handler device, and an internal
bus operably coupled to the memory, the bridge communication
device, the processor, and the interrupt handler device;

the bridge communication device configured to receive the first
interrupt message and to transmit the first interrupt message to
the interrupt handler device;
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the interrupt handler device further configured to send the first
interrupt message through the internal bus to the memory to
store the first interrupt message in a first memory location in
the memory, the interrupt handler device further configured to
transmit a first signal to the processor indicating that the first
interrupt message has been stored in the memory; and

the processor configured to retrieve the first interrupt message
from the memory in response to the first signal and to perform
at least one task associated with the first interrupt message.

The References
The Examiner relies on the following references as evidence:
Nissen US 4,591,977 May 27, 1986
Mackey US 2003/0088723 A1 May 8, 2003

The Rejection
The following rejection is before us for review:
Claims 1-8, 10, 14, and 16-21 stand rejected under 35 U.S.C. § 103(a)
as being unpatentable over the combination of Mackey and Nissen.
Only those arguments actually made by the Appellants have been
considered in this decision. Arguments which the Appellants could have
made but chose not to make in the Briefs have not been considered and are
deemed to be waived. See 37 C.F.R. § 41.37 (c)(1)(vii) (2008).

II. ISSUE
Has the Examiner erred in finding that the combination of Mackey and
Nissen teaches or fairly suggests “an internal bus operably coupled to the
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memory, the bridge communication device, the processor, and the interrupt
handler device,” as recited in claim 1?

III. PRINCIPLES OF LAW
Scope of Claims
During prosecution before the USPTO, claims are to be given their
broadest reasonable interpretation, and the scope of a claim cannot be
narrowed by reading disclosed limitations into the claim. See In re Morris,
127 F.3d 1048, 1054 (Fed. Cir. 1997). Giving claims their broadest
reasonable construction “serves the public interest by reducing the
possibility that claims, finally allowed, will be given broader scope than is
justified.” In re Yamamoto, 740 F.2d 1569, 1571 (Fed. Cir. 1984)).
Obviousness
“Obviousness is a question of law based on underlying findings of
fact.” In re Kubin, 561 F.3d 1351, 1355 (Fed. Cir. 2009). The underlying
factual inquiries are: (1) the scope and content of the prior art, (2) the
differences between the prior art and the claims at issue, (3) the level of
ordinary skill in the pertinent art, and (4) secondary considerations of
nonobviousness. KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 406 (2007)
(citation omitted).

IV. FINDINGS OF FACT
The following findings of fact (FFs) are supported by a preponderance
of the evidence.
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Specification
1. The Specification discloses that “the interrupt handler device 34
writes the interrupt message to a predetermined address in the memory 36.
In an alternate embodiment, the interrupt handler device 34 writes the
interrupt message to a predetermined address in the memory 32.” ([0017],
Fig. 2).
Mackey
2. Mackey discloses that an interrupt service queue is formed (108, Fig.
2) after the interrupt handler 22 determines an interrupt signal input is
unavailable (104, Fig. 2). The interrupt service queue is inherently stored in
a buffer or other type memories to hold the received interrupt messages
([0031]-[0032]; Fig. 2).
3. Mackey also discloses the device 12 comprises a main controller 12
with at least on processor ([0024]), a bridge 8 ([0023]), an interrupt message
receiver 18 for maintaining a door-bell register ([0028]), an interrupt
controller 22 for allocating the resources of the main controller 14 to service
received interrupt messages ([0030]), and an internal bus 4 directly
connecting the bridge 8, the interrupt message receiver ([0021]) or the
interrupt controller ([0029]), and the interrupt sources 10 ([0021]).
Nissen
4. Nissen discloses that an internal bus directly connects a processor 10a
and a local memory 12a (Fig. 3).

V. ANALYSIS
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Appellants have the opportunity on appeal to the Board of Patent
Appeals and Interferences (BPAI) to demonstrate error in the Examiner’s
position. See In re Kahn, 441 F.3d 977, 985-86 (Fed. Cir. 2006) (citing In re
Rouffet, 149 F.3d 1350, 1355 (Fed. Cir. 1998)).
The Examiner set forth a detailed explanation of a reasoned
conclusion of unpatentability in the Examiner’s Answer. Therefore, we look
to the Appellants’ Brief to show error in the proffered reasoned conclusion.
See Kahn, 441 F.3d at 985-86 (citing Rouffet, 149 F.3d at 1355).
Grouping of Claims
Appellants have elected to argue claims 1-8, 10, 14, and 16-21
together as a group (App. Br. 9) and have presented similar arguments for
all independent claims (Id. at 11-12). Therefore, we select independent
claim 1 as the representative claim for this group, and we will address
Appellants’ arguments with respect thereto. 37 C.F.R. § 41.37 (c)(1)(vii).
See In re Nielson, 816 F.2d 1567, 1572 (Fed. Cir. 1987).
35 U.S.C. § 103(a) rejection
With respect to claim 1, the Appellants contend that “[f]rom the
specific language of claim 1, it is clear that the cited interrupt handler device
is distinct from the memory. In other words, the memory is not the interrupt
handler device or a part of the interrupt handler device.” (App. Br. 9). In
particular, it is improper under the rules of claim construction to interpret the
interrupt controller 22 as “both the ‘interrupt handler device’ and the
‘memory’ of claim 1 since both are separately recited elements.” (Id. at 10).
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We disagree with the Appellants’ contentions. The Office must apply
the broadest reasonable meaning to the claim language, taking into account
any definitions presented in the Specification. In re Am. Acad. of Sci. Tech.
Ctr., 367 F.3d 1359, 1364 (Fed. Cir. 2004) (citing In re Bass, 314 F.3d 575,
577 (Fed. Cir. 2002)). Here, we find that the claim language of claim 1 does
not limit the location of the memory in the first device claimed or the type of
the memory (see representative claim 1). Moreover, we also find that the
Specification describes two embodiments that 1) the memory 36 is located
inside of the interrupt handler device 34; and 2) the memory 32 is separate
from the interrupt handler 34 and connected to internal bus 30 (FF 1). We
thus broadly yet reasonably construe the claim limitations “interrupt handler
device” and “memory” as disclosing either an interrupt handler device
having a memory or an interrupt handler device with a separate memory as
there is no limitation in the claim language to prevent us from reading these
claimed terms broadly. Finally, we agree with the Examiner’s claim
construction, finding that the interrupt controller 22 and the interrupt service
queue can be construed as the interrupt handler device and the memory
recited in claim 1 (FF 1 and FF 2).
The Appellants further contend that neither Mackey nor Nissen
provides any teaching of “the interrupt handler device further configured to
send the first interrupt message through the internal bus to the memory to
store the first interrupt message in a first memory location in the memory.”
(App. Br. 10).
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We disagree with the Appellants’ contention. We find that the
interrupt messages are stored in the queue (FF 2). According to the first-in
first-out (FIFO) characteristic of the queue, Mackey teaches that the first
interrupt message will be inherently stored in a first memory location of the
memory stored in the queue and the second interrupt message will be
inherently stored in a second memory location of the memory stored in the
queue (FF 2).
The Appellants also contend that: 1) neither Mackey nor Nissen
provides any teaching of “an internal bus operably coupled to the memory,
the bridge communication device, the processor, and the interrupt handler
device” recited in claim 1 (App. Br. 10); 2) “the proposed combination
would destroy the primary functionality of the Mackey et al. system wherein
the interrupt controller 22 and the internal interrupt receiver 18 prevent the
main controller 14 from being inundated with interrupt messages that could
not be processed immediately.” (Id. at 8).
We disagree with the Appellants’ contentions. First, we find that
Mackey teaches all the claimed elements (FF 3) except the internal bus
directly connects a processor or a memory. We also find that Nissen teaches
that a bus connects a processor and a memory (FF 4).
Furthermore, “if a technique has been used to improve one device,
and a person of ordinary skill in the art would recognize that it would
improve similar devices in the same way, using the technique is obvious
unless its actual application is beyond his or her skill.” KSR, 550 U.S. at 417.
Here, the use of an internal bus to directly connect a processor and a
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memory of Nissen was well known to improve the processing speed of a
computer. One of ordinary skill in the art would recognize that Nissen’s
method would improve the similar system of Mackey in the same or a
similar way. We find that the combination of Mackey and Nissen is “a
design step well within the grasp of a person of ordinary skill in the relevant
art” (id. at 427) because connecting the processor and memory of Mackey to
the internal bus would not affect any functionality of handling the interrupt
of Mackey (since there is no modification of the interrupt handler controller
or interrupt message receiver) but would only improve the processing speed
of Mackey’s system. The Appellants have not shown that employing the
technique of Nissen in the interrupt handler device of Mackey would be
uniquely challenging or difficult for one of ordinary skill in the art or would
represent an unobvious step over the prior art. We therefore find that
combining the well-known elements of Nissen with the well-known
technique of handling the interruption of a computer taught by Mackey is
nothing more than a “predictable use of prior art elements according to their
established functions.” KSR, 550 U.S. at 417.
Accordingly, we sustain the Examiner’s obviousness rejection of
independent claim 1. We also sustain the Examiner’s obviousness rejection
of the independent claims 16 and 20, for which the Appellants present
similar arguments. We also sustain the Examiner’s obviousness rejection of
dependent claims 2-8, 10, 14, 17-19, and 21, which have analogous wording
and are not separately argued, and which therefore fall with their respective
base claims. 37 C.F.R. § 41.37 (c)(1)(vii). See In re Nielson, 816 F.2d at
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1572.
VI. CONCLUSION
Based on our consideration of the totality of the record before us, we
have weighed the evidence of obviousness found in the combined teachings
of the applied references with Appellants’ countervailing evidence and
arguments for nonobviousness and conclude that the claimed invention
encompassed by appealed claims 1-8, 10, 14, and 16-21 would have been
obvious as a matter of law under 35 U.S.C. § 103(a).

VII. ORDER
We affirm the obviousness rejection of claim 1-8, 10, 14, and 16-21
under 35 U.S.C. § 103(a).

No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136 (a). See 37 C.F.R.
§ 1.136(a)(1)(iv).
AFFIRMED

erc

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