Ex Parte Davies et al

Board of Patent Appeals and Interferences

May 17, 2010

10116245 (B.P.A.I. May. 17, 2010)

UNITED STATES PATENT AND TRADEMARK OFFICE
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BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
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Ex parte ANDREW DOUGLAS DAVIES and DANIEL
LAWRENCE STASIAK
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Appeal 2009-004552
Application 10/116,245
Technology Center 2100
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Decided: May 18, 2010
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Before JAMES D. THOMAS, JOSEPH L. DIXON, and STEPHEN C. SIU,
Administrative Patent Judges.

THOMAS, Administrative Patent Judge.

DECISION ON APPEAL

STATEMENT OF THE CASE
Appeal 2009-004552
Application 10/116,245

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This is an appeal under 35 U.S.C. § 134(a) from the Examiner’s final
rejection of claims 4-12 and 16. Appellants have cancelled claims 1-3 and
13-15. We have jurisdiction under 35 U.S.C. § 6(b).
We affirm.

Invention
A method and apparatus are provided for implementing
dynamic noise immunity and minimizing delay of
complementary metal oxide semiconductor (CMOS) logic
circuits. A method of logical effort is applied to the CMOS
logic circuits. Selected circuits within the CMOS logic circuits
are checked for noise immunity utilizing a noise test simulation
to identify each selected circuit failing the noise test simulation.
An electrical effort is fixed to a value for providing noise
immunity for each identified selected circuit failing the noise
test simulation. The method of logical effort is applied to each
remaining selected circuit not failing the noise test simulation.
The sequential steps are repeated for each remaining selected
circuit not failing the noise test simulation until no selected
circuit failing the noise test simulation is identified.

(Abstract, Spec. 15, ll. 4-15, Figs. 2-4.)
Representative Claim
4. A computer implemented method for implementing noise immunity and
minimizing delay of complementary metal oxide semiconductor (CMOS)
logic circuits comprising the steps of:

applying a method of logical effort to the CMOS logic circuits;

checking selected circuits within said CMOS logic circuits for noise
immunity utilizing a noise test simulation to identify each selected circuit
failing said noise test simulation;

modifying each identified selected circuit failing said noise test
simulation for providing noise immunity by fixing an electrical effort of
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each identified selected circuit failing said noise test simulation to a value
for providing noise immunity including varying device widths of devices
within predefined stages of each identified selected circuit failing said noise
test simulation including reducing device widths of N-channel devices
within a first stage and increasing device widths of at least one N-channel
and at least one P-channel devices within a second stage of each identified
selected circuit failing said noise test simulation; and

storing the modified identified selected circuits within said CMOS
logic circuits.

Prior Art and Examiner’s Rejection
Claims 4-12 and 16, which constitute all claims on appeal, stand
rejected under 35 U.S.C. § 103. As evidence of obviousness, the Examiner
relies upon Shepard in view of Cohn:
Cohn 6,490,708 B2 Dec. 3, 2002
(filed Mar. 19, 2001)

K.L. Shepard et al., Design Methodology for the S/390 Parallel Enterprise
Server G4 Microprocessors, 41 IBM J. RES. DEVELOP. No. 4/5, 515-547
(1997) (“Shepard”).

Claim Groupings
Based upon Appellants’ arguments in the Appeal Brief, although
Appellants appear to argue independent claims 4, 9, and 16 separately, it
appears that the same arguments are made with respect to a commonly
recited feature among each of these independent claims. Separate arguments
are presented as to dependent claims 5 and 11 on appeal. No other claim is
argued.

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ISSUE
Did the Examiner err in finding that the combination of Shepard and
Cohn teaches the ability to vary device widths, including reducing device
widths and increasing device widths, within different staged electrical
devices?

FINDINGS OF FACT (“FF”)
1. Appellants’ discussion of the prior art at Specification page 1, lines 9-
18 indicates that the so-called method of logical effort relates to
designing CMOS logic circuits that provide a way to minimize delays
within the circuits using concepts of logical effort, electrical effort,
and effort delay. It is known in the art that the method of logical
effort provides a method of choosing the sizes of the transistors in the
circuits so that a delay from the input to the output circuits is
minimized. This has been recognized in a prior art book noted by
Appellants. Specification page 4, lines 22-28 utilized this book by
making specific references to chapters 1 and 3 of it. Appellants also
assert in the paragraphs bridging pages 1 and 2 of the Specification as
filed that this method has no provisions for addressing dynamic noise
immunity.
2. Shepard’s design methodology includes significant teachings relating
to minimizing noise and, therefore, increasing noise immunity as the
Examiner has noted in the Answer. Column 2 at page 532 of Shepard,
as noted by the Examiner, recognizes and utilizes logical effort and
electrical effort for which specific prior art documents have been
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referenced in Shepard’s publication. The second column of page 542
begins a lengthy discussion of noise analysis to directly address
leakage noise, power-supply noise, charge-sharing noise, and cross
talk noise. Moreover, topic 10 at page 545 of Shepard concludes this
document in this manner:
10. Conclusions
In this paper we have reviewed the philosophies,
techniques, and processes used in the design of the S/390
Parallel Enterprise Server G4 microprocessor. In doing so,
we have emphasized some of the guiding themes of our
approach. Cycle simulation is an essential element of any
verification effort, and a methodology must exist to map
the design from an event-driven HDL into a cycle simulation
model or, in many cases, into multiple cycle simulation
models. The design methodology must be fundamentally
transistor-level to allow detailed optimization trade-offs among
timing, power, and noise. At the same time, to manage the
complexity, a consistent two-level hierarchical approach must
be used for all key analysis processes, with design abstractions
stored and controlled from a common database. Static
techniques must be employed for these analyses wherever
possible. In addition, one of these analyses must be noise,
which has acquired overwhelming importance with technology
scaling.

3. In like manner, Cohn is also concerned with increasing noise
immunity as revealed in his Abstract as well as initial discussions at
columns 1 and 2 of this patent. Significantly, Cohn teaches the
following:
One approach to fixing the noise/timing problem is to adjust
various parameters of the system such as spacing, power, and
cell size. Spacing adjustments, for example, are effective
because they change the coupling capacitance between adjacent
conductors. In other words, because noise can be coupled from
one conductor to another by their mutual capacitance,
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increasing the separation between these wires reduces coupling
capacitance and therefore reduces the amount of noise injected.

The effects of such changes or adjustments, whether to spacing,
power, or some other parameter, can be predicted with
reasonable accuracy; the difficulty lies in the fact that it is
nearly impossible to predict exactly which change out of an
uncountably large number of possible changes is necessary to
fix a specific problem. Trial and error, therefore, becomes the
only currently viable solution approach, but is itself severely
flawed. Besides being inefficient and time consuming, it is ill-
equipped to discover problems early in the chip design process.
Yet noise sensitivity problems are best discovered as early in
the design process as possible in order to avoid the costs of
redesign or reconstruction activity.

(Col. 2, ll. 19-40.)
Cohn’s approach is to utilize cell libraries to minimize an actual
trial and error process; as recognized at column 9, lines 8 and 9, “the
repetitive process described is one of, but not the only, acceptable
solution.” Because of its importance here, we also reproduce column 10,
lines 10-27, which is relied upon by the Examiner:
It is often the case that a cell may have different noise immunity
depending on the polarity of the impinged noise pulse. This is
controlled by the type of circuitry and the manufacturing
process. Separate noise signals for positive going and negative
going noise apply to each net and yield different results when
compared to the cells' polarity-dependent noise
rejection. This polarity dependence can be advantageous to the
noise correction process. Increasing nfet device width while
decreasing pfet device width (and vice versa) results in a cell
with improved noise tolerance to negative going noise at the
expense of tolerance to positive going noise. The cell's input
capacitance is not changed if the total nfet and pfet device
width remains constant. Similarly, exchanging high Vt devices
for standard Vt devices will yield improved noise tolerance and
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neutral input capacitance at the expense of cell delay and
potentially increased manufacturing costs to support the
different Vt device.

ANALYSIS
We refer to, rely on, and adopt the Examiner’s findings and
conclusions set forth in the Answer. Our discussions will be limited to the
following points of emphasis.
According to the teachings we noted in FF1, Appellants viewed the
prior art approaches regarding the use of the logical effort concepts of
CMOS circuit design to have no provisions to address dynamic noise
immunity. On the other hand, the portions of FF2 we have identified in
Shepard clearly indicate that this reference utilizes the methodology of
logical effort and electrical effort to minimize noisy CMOS circuits.
The manner in which noise is minimized in such circuits is not
detailed in Shepard. These details are set forth in Cohn as we have noted at
FF 3. To the extent that the argued features allegedly are not found among
their combination, those that we have reflected in our issue statement in this
opinion, they are sufficiently taught within the combination to have rendered
obvious the subject matter of representative independent claim 4 that have
been argued before us. Corresponding features are found in a slightly
broader manner in independent claims 9 and 16 on appeal.
Moreover, to the extent the repetitive and iterative nature of the last
clause of independent claim 16 on appeal is argued in the Brief, the
significant teachings in Cohn as well as those summarized in the conclusion
portion of Shepard clearly indicate that there is a repetitive and analytical
approach to the logical effort to increasing noise immunity and CMOS logic
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circuits. This is reflected in the teachings of cyclic simulation and
optimization of design trade-offs. This analysis as well as the Examiner’s
analysis in the Answer is consistent with our reviewing Court’s analysis set
forth in Ritchie v. Vast Resources. 563 F.3d 1334 (Fed. Cir. 2009).
In many respects, this case indicates that routine experimentation to optimize
result effective variables, such as reflected in the argued features allegedly
not found in the combination, are a normal part of the skill set of a person of
ordinary skill in the art within 35 U.S.C. § 103. Special reliance is placed on
the United States Supreme Court’s decision in KSR Int'l Co. v. Teleflex Inc.,
550 U.S. 398 (2007) in the Court’s analysis in Ritchie.
Lastly, we address the features of dependent claims 5 and 11. These
claims merely reflect logical extensions of the logical effort approach to
CMOS logic circuit design to circuits that did not fail noise test simulation,
since the logical effort within this technology requires a complete circuit
analysis and re-analysis when any changes are made, even including those
circuits not initially failing a noise test simulation.
No Reply Brief has been filed in this appeal contesting Examiner’s
lengthy responsive arguments in the Answer that directly address
Appellants’ arguments in Appeal Brief.

CONCLUSION AND DECISION
Appellants have not shown that the Examiner erred in finding that the
combination of Shepard and Cohen teach the features of varying device
widths by reducing and increasing device widths within respective stages of
an overall circuit. The Examiner’s rejection under 35 U.S.C. § 103 of claims
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4-12 and 16, all claims on appeal, is affirmed. All claims on appeal are
unpatentable.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

AFFIRMED

erc

Robert R. Williams
IBM Corporation - Dept. 917
3605 Highway 52 North
Rochester, MN 55901